MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 151
MT9072
Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9072.pdf
(278 pages)
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Advance Information
Bit
9
8
7
6
5
4
3
2
1
0
Name
F6RM
F6SM
F5HM
F5EM
F5RM
F5SM
F4HM
F4EM
F4RM
F4SM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Framer 6 Rx LineMask. This is the mask bit for the F6RVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 6 Sync and Overflow Mask. This is the mask bit for the F6SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 5 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 5 Elastic Mask. This is the mask bit for the F5EVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 5 Rx Line Mask. This is the mask bit for the F5RVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 5 Sync and Overflow Mask. This is the mask bit for the F5SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 4 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 4 Elastic Mask. This is the mask bit for the F4EVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 4 Rx Line Mask. This is the mask bit for the F4RVS status bit in the Interrupt Vector
register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 4 Sync and Overflow Mask. This is the mask bit for the F4SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Table 126 - Interrupt Vector 2 Mask Register (Address 903) (T1)
Functional Description
MT9072
151
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