MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 71

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
and inhibiting of Tx CRC for terminal adaptation is also provided. The HDLC controller has two 32 byte deep
FIFO’s associated with it; one for Transmit and one for Receive.
8.1.1
A valid HDLC frame begins with an opening flag, contains at least 16 bits of address and control or information,
and ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner is also referred to as a
“packet”. Refer to Table 33.
All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags
and appends them to the packet to be transmitted. The receiver searches the incoming data stream for the
flags on a bit- by-bit basis to establish frame synchronization.
The data field consists of an address field, control field and information field. The address field consists of one
or two bytes directly following the opening flag. The control field consists of one byte directly following the
address field. The information field immediately follows the control field and consists of N bytes of data. The
HDLC does not distinguish between the control and information fields and a packet does not need to contain an
information field to be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CRC-CCITT standard generator polynomial “X
FCS is calculated on all bits of the address and data field. The complement of the FCS is transmitted, most
significant bit first, in the FCS field. The receiver calculates the FCS on the incoming packet address, data and
FCS field and compares the result to “F0B8”. If no transmission errors are detected and the packet between
the flags is at least 32 bits in length then the address and data are entered into the receive FIFO minus the
FCS which is discarded.
8.1.2
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of 5 contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
8.1.3
A frame is invalid if one of the following four conditions exists (Inserted zeros are not part of a valid count):
•
•
•
•
8.1.4
The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of
the normal packet. The receiver will abort upon reception of seven contiguous 1s occurring between the flags
of a packet which contains at least 25 bits.
Note that should the last received byte before the frame abort end with contiguous 1s, these are included in the
seven 1s required for a receiver abort. This means that the location of the abort sequence in the receiver may
One Byte
01111110
If the FCS pattern generated from the received data does not match the “F0B8” pattern then the last
data byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the
receiver and nothing is written to the receive FIFO.
Packets which are at least 26 bits in length but less than 32 bits between the flags are also invalid. In
this case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.
If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside
in the receive FIFO, assuming the packet length before the abort sequence was at least 25 bits long.
Flag (7E)
Data Transparency (Zero Insertion/Deletion)
HDLC Frame Structure
Invalid Frames
Frame Abort
n Bytes
n
Table 33 - HDLC Frame Format
Data Field
16
+X
12
+X
5
+1” produces the 16-bit FCS. In the transmitter the
Two Bytes
FCS
One Byte
01111110
MT9072
Flag (7E)
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