MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 143

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
16.1.8
Tables 116 to 122 describe the bit functions of each of the Master Control Registers in the MT9072 for T1
mode. Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1,
Framer 2 with Y=2,... Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A
A
A8 to 0. A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a hard
reset (the RESET pin is toggled from zero to one), or a software reset (the RST bit in control register address
YF1 is toggled from one to zero or toggling of RSTC in Global Control Register). The (#) indicates that a (0) or
(1) is possible.
15-11
9
Bit
10
A
9
8
7
6
5
4
3
2
1
0
8
). In addition, a simultaneous write to all 8 Framers is possible by setting the address A11 to 1 and A10 to
Master Control Registers (YF1 to YF7) Bit Functions
TXMFSEL
CNTCLR
SAMPLE
DSToEN
CSToEN
Tx8KEN
SPND
Name
RxDO
RxCO
INTA
RST
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
not used.
Transmit 8 KHz Enable. If one, the pin RxMF transmits a positive 8 KHz frame pulse
synchronous with the serial data stream TPOS/TNEG. If zero, the pin RxMF transmits a
negative frame pulse synchronous with the multiframe boundary of data coming out of DSTo.
Receive DSTo All Ones. If one, the DSTo pin operates normally. If zero, all timeslots (0-31)
of DSTo are set to one.
Transmit Multiframe Select. This bit is used to select if the framer is used for application of
the TXMF pulse which sets the multiframe boundary for the T1 transmitters. A one will select
the framer for application of TXMF.
Suspend Interrupts. If zero, the IRQ output will be in a high-impedance state and all
interrupts will be ignored. If one, the IRQ output will function normally.
Interrupt Acknowledge. All interrupt and latched status registers for a particular framer
may be cleared (without reading the interrupt status registers) by setting the INTA control bit
to zero. Interrupt status registers for a particular framer will be cleared (and not updated) as
long as INTA is low. The framers interrupt vector bits will remain at zero, therefore that
framer cannot toggle the IRQ pin.
DSTo Enable. If zero, pin DSTo is tristate. If set, pin DSTo is enabled.
CSTo Enable. If zero, pin CSTo is tristate. If set, pin CSTo is enabled.
Receive CSTo All Ones.If one, the CSTo pin operates normally. If zero all timeslots of CSTo
are set to one
Counter Clear. When this bit is changed from zero to one, all non-latched status counters
(address Y15 to Y1A) are cleared. If zero, all non-latched status counters operate normally.
One Second Sample. Setting this bit causes the latched error counters(Y28 to Y2C)
(change of frame alignment, loss of frame alignment, bpv errors, crc errors, severely errored
frame events and multiframes out of sync) to be updated on one second intervals coincident
with the one second timer (Y11).
Reset. When this bit is changed from zero to one, the selected framer (Y) will reset to its
default mode. The default mode will depend on the T1E0 bit(Global control0 bit 15). Any
write to his bit should be followed by 125 usec before initialization of per timeslot control etc.
See the Reset Operation section for the default settings.
Table 116 - Interrupt and I/O Control(YF1) (T1)
Functional Description
MT9072
11
A
143
10