MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 208

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
16.2.9
Table 191 describes the bit functions of each (30 registers in total, one register for each PCM 30 channel) of
the Receive CAS Data Registers in the MT9072. Each register is repeated for each of the 8 framers. Framer 0
is addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y
represents the 4 most significant address bits (MSB) A11-A8).
A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET,
RSTC or RST). The (#) indicates that a (0) or (1) is possible.
208
15-4
For these functions to be valid, CAS mode must be selected (CSIG=0 register address Y03).
Bit
3
2
1
0
(#### #### ####)
Receive CAS (ABCD) Data Registers (Y71 - Y8F) Bit Functions
Name
A
B
C
D
(#)
(#)
(#)
(#)
(n)
(n)
(n)
(n)
Table 191 - Channel n, Receive CAS Data Register (Address Y71-Y8F)
not used.
Receive Channel Associated Signaling (CAS) Signaling Bits for Channel 1 to 30.
Bits for n=1 to 15 correspond to channel 1 to 15 and are received on the PCM30
link in timeslot 16 in bit positions one to four in frame n.
Bits for n=17 to 31 correspond to channel 16 to 30 and are received on the PCM30
link in timeslot 16 in bit positions five to eight in frame n -16.
Functional Description
Advance Information