MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 127

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
15-0
Bit
15-7
7-0
Bit
5-4
3-2
1-0
Bit
6
RCRC15-0 Received CRC. This register contains the CRC received from the transmitter. These bits
RXFIFO7-0
RXSTAT1-0 Receive FiFO Status:
TXSTAT1-0 Transmit FiFO Status:
Name
Name
RQ9-8
Name
IDC
#
are as the transmitter sent them, the LSB of the FCS sequence is MSB in this register. This
register is updated at the end of each received packet and therefore should be read when
end of packet is detected.
Receive FIFO.This is the received data byte read from the RX FIFO. The status bits of
this byte can be read from the status register. The FIFO status is not changed
immediately when a write or read occurs. It is updated after the data has settled and the
transfer to the last available position has finished.
Note that if the HDLC receiver is connected to an receive T1 channel, the bit that arrived
first is stored in the least significant bit of the receive FIFO.
not used.
Idle Channel State.Is set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may be 1 if
the clock (RXC) was not operating. Status becomes valid after the first 15 bits or the first
zero is received.
RQ9-8Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
00 Packet Byte
01 First Byte
10 Last byte of good packet
11 Last byte of bad packet
00 Transmit FIFO is full.
01 The number of bytes in the transmit FIFO has reached or exceeded the 16 bytes
threshold
10 Transmit FIFO is empty
11 The number of bytes in the TX FIFO is less than the 16 byte threshold.
00 Receive FIFO is empty.
01 The number of bytes in the Receive FIFO are less than the 16 bytes
10 Receive FIFO is full
11 The number of bytes in the Receive FIFO is greater than or equal to the 16 byte
threshold.
Table 94 - HDLC Receive CRC(Y1E) (T1)
Table 93 - HDLC Status Word(Y1D) (T1)
Table 95 - Receive FIFO(Y1F) (T1)
Functional Description
Functional Description
Functional Description
MT9072
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