MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 56

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
programmed by writing to Tx Set Delay Bits (register address YF7). Every write to the TX Set Delay Bits resets
the Transmit Slip Buffer MSB bit TxSBMSB (register address Y14). After a write, the delay through the slip
buffer is less than 1 frame in duration. Each write operation will result in a disturbance of the transmit PCM24
frame boundary, causing the far end to go out of sync.
The transmit elastic buffer is capable of performing controlled slips in a manner similar to the receive elastic
buffer. Slips on the transmit side are independent of slips on the receive side. The two status bits. TSLIP and
TSLPD (register address Y14), give indication of a slip occurrence and direction. TSLP changes state in the
event of a slip. If TSLPD=0, the slip buffer has overflowed and a frame was lost; if TSLPD=1, an underflow
condition occurred and a frame was repeated. A maskable interrupt status bit TXSLIPI (register address Y36)
is also provided. Under normal operation no slips should occur in the transmit path. Slips will only occur if the
input CKi clock has excess wander relative to the input TXCL clock, or if the TX Set Delay Bits (register
address YF7) register is initialized too close to the slip pointers after system initialization.
6.0
6.1
The ESF protocol allows for carrier messages to be embedded in the S-bit position. The MT9072 provides 3
separate means of controlling the Data Link.
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•
•
In the D4 mode the Fs bits can be inserted/extracted from the Data Link pins by setting the EDLEN bit in Y06.
The registers related to the Data Link are shown in Table 16.
56
Register
Address
Transmit and receive Data Link pins TxDL, TxDLC, RxDL and RxDLC.
Bit - Oriented Messages may be transmit and received via dedicated transmit and receive
registers(Y07,Y08,Y12). This is only applicable in the ESF mode.
The ESF Data Link (DL) can be connected to an internal HDLC, operating at a bit rate of 4 kbits/sec.
The HDLC can be activated by setting the control bit 1(HDLCEn) of the HDLC & Data Link Control Word
(Y06).
Y06
Y07
Y08
Y12
Y25
Y35
Y45
T1 Data Link
Data Link
HDLC and Data Link Control
Register
Transmit bit Oriented Message This register holds the message that will be sent in ESF FDL if the
Receive bit Oriented Message
Match
Receive bit Oriented Message This register holds the value of the receive bit oriented message
Receive Line Status and Timer
Latch
Receive Line and Timer
Interrupt Status
Receive Line and Timer
Interrupt Mask
Table 16 - Registers Related to the Data Link and Bit Oriented Messages (T1)
Register
This register determines the source of the Data Link which can be
the HDLC, Bit Oriented messages or the external Data Link. This
register also controls the type of clocks provided to the external
Data Link interface.
BOMEN bit in Y06 is set.
This register is the match register for received bit oriented message
This register contains bit oriented message and bit oriented
message match latch bits.
This register contains bit oriented message and bit oriented
message match interrupt status bits.
These are the mask bits for Y35.
Description
Advance Information