MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 44

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
3.2
Register control bits COD1-0 (address Y02) determine the format of the PCM30 transmit and receive signals.
Three interface formats are provided including RZ dual rail, NRZ dual rail and NRZ single rail.
RZ Dual Rail - On the Transmit side the pulse width is approximately half the duration of the PCM30 bit cell
centered around the falling edge of TXCL. On the receive side RPOS and RNEG are sampled on the falling
edge of EXCLi. Note that the T2OP bit in Register Y02(selectable for edge sampling) has no effect in RZ mode.
NRZ Dual Rail - With this format, pulses are present for the full bit cell, which allows the set-up and hold times
to be easily met. For the receiver the sampling point can be the rising edge or the falling edge of the EXCLi
clock dependent on the CLKE bit in Register Y01. The transmitted data can be output either on the rising or
falling edge of TXCL selected by the T2OP bit. TXCL is an input in T1 mode and output in E1 mode.
NRZ Single Rail - This NRZ format is not dual rail, and therefore, only requires a single output line and a single
input line (i.e., TPOS and RPOS). The T2OP bit controls the TXCL clock edge and CLKE bit controls the
RPOS/RNEG sampling.
HDB3 - Register Control bit THDB3 (address Y02) determines the PCM30 encoding in the transmit direction.
The encoding can either be HDB3 or alternate mark inversion (AMI). The RHDB3 (address Y02) bit selects the
receive HDB3 decoding.
4.0
4.1
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit - the S-bit. The S-bit
contains a fixed repeating pattern used to enable DS1 receivers to delineate frame boundaries. S-bits are
inserted once per frame at the beginning of the transmit frame boundary. The DS1 frames are further grouped
in bundles of frames, generally 12 (for D4 applications) or 24 frames deep (for ESF - extended superframe
applications). The registers for controlling and observing the framing algorithms are presented in the Table 7.
44
E1 Interface to the Physical Layer Device
T1 Framing
Framing
FRAME
15
FRAME
Significant
Bit (First)
0
Most
TIMESLOT
BIT
0
1
• • • • • • • •
BIT
2
Figure 6 - PCM30 Format (E1)
TIMESLOT
1
BIT
3
2.0 ms
BIT
(8/2.048) s
4
• • • •
BIT
5
125 s
BIT
6
FRAME
14
BIT
7
TIMESLOT
BIT
30
8
FRAME
15
Least
Significant
Bit (Last)
Advance Information
TIMESLOT
31
FRAME
0