mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 12

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mt48lc1m16a1

Manufacturer Part Number
mt48lc1m16a1
Description
Synchronous Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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OPERATION
BANK/ROW ACTIVATION
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
mand) a READ or WRITE command may be issued to
that row, subject to the
(MIN) should be divided by the clock period and
rounded up to the next whole number to determine
the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be issued. For
example, a
clock (8ns period) results in 2.5 clocks rounded to 3.
This is reflected in Figure 4, which covers any case where
2 <
to convert other specification limits from time units to
clock cycles.)
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
can be issued while the first bank is being accessed, which
results in a reduction of total row access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
Before any READ or WRITE commands can be
After opening a row (issuing an ACTIVE com-
A subsequent ACTIVE command to a different row
A subsequent ACTIVE command to another bank
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz
COMMAND
t
EXAMPLE: Meeting
CK ≤ 3. (The same procedure is used
CLK
t
RCD specification.
ACTIVE
T0
t
t
RC.
RRD.
t
RCD (MIN) when 2 <
NOP
T1
t
RCD
Figure 4
t
RCD
12
T2
A0-A10
NOP
CAS#
RAS#
WE#
CKE
CLK
CS#
BA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Activating a Specific Row
t
RCD (MIN)/
HIGH
in a Specific Bank
READ or
WRITE
T3
Figure 3
DON’T CARE
t
CK ≤ ≤ ≤ ≤ ≤ 3
ADDRESS
BANK 1
BANK 0
ROW
T4
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.

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