mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 16

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

a subsequent WRITE command, and data from a
fixed-length READ burst may be immediately followed
by data from a subsequent WRITE command (subject
to bus turnaround limitations). The WRITE burst may
be initiated on the clock edge immediately following
the last (or last desired) data element from the READ
burst, provided that I/O contention can be avoided. In
a given system design, there may be the possibility that
the device driving the input data would go Low-Z
before the SDRAM DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read
data and the WRITE command.
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks (DQM latency is
two clocks for output buffers) prior to the WRITE
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
Data from any READ burst may be truncated with
The DQM input is used to avoid I/O contention as
COMMAND
ADDRESS
NOTE:
DQM
CLK
DQ
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
T0
BANK,
COL n
READ
READ to WRITE
Figure 9
T1
NOP
T2
NOP
T3
NOP
D
t HZ
OUT
t CK
n
BANK,
T4
COL b
WRITE
D
IN
b
t
DS
16
command to suppress data-out from the READ. Once
the WRITE command is registered, the DQs will go
High-Z (or remain High-Z) regardless of the state of the
DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated
the READ command. If not, the second WRITE will be
an invalid WRITE. For example, if DQM was LOW
during T4 in Figure 10, then the WRITEs at T5 and T7
would be valid, while the WRITE at T6 would be
invalid.
is zero clocks for input buffers) prior to the WRITE
command to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency
allows for bus contention to be avoided without add-
ing a NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
COMMAND
ADDRESS
The DQM signal must be de-asserted (DQM latency
NOTE:
DQM
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
BANK,
COL n
T0
READ
READ to WRITE with
Extra Clock Cycle
T1
NOP
Figure 10
T2
NOP
T3
NOP
t HZ
D
OUT
16Mb: x16
n
IT SDRAM
T4
©1999, Micron Technology, Inc.
NOP
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS