mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 42

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mt48lc1m16a1

Manufacturer Part Number
mt48lc1m16a1
Description
Synchronous Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
SYMBOL*
t
t
t
t
t
t
t
t
t
t
t
AH
CH
AC (3)
AC (2)
AC (1)
AS
CL
CK (3)
CK (2)
CK (1)
CKH
DQM
A0-A9
A10
CLK
CKE
DQ
BA
3
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
t CMS
t CKS
t AS
t AS
t AS
MIN
2.5
2.5
20
ACTIVE
BANK 0
1
2
6
8
1
T0
ROW
ROW
t CMH
t CKH
t AH
t AH
t AH
-6
MAX
t RCD - BANK 0
t RAS - BANK 0
t
t
5.5
18
RC - BANK 0
RRD
8
t CK
T1
MIN
2.75
2.75
NOP
10
25
1
2
7
1
-7
ENABLE AUTO PRECHARGE
MAX
5.5
8.5
22
ALTERNATING BANK READ ACCESSES
t CMS
t CL
COLUMN m
(A0 - A7)
BANK 0
T2
READ
t CMH
MIN
t CH
13
25
1
2
3
3
8
1
2
CAS Latency - BANK 0
-8A
MAX
22
6
9
T3
NOP
t LZ
UNITS
t AC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
BANK 1
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
m
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
CMH
RAS
RC
RCD
RP
RRD
CKS
CMS
LZ
OH
t RCD - BANK 1
D
T5
OUT
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
m + 1
t OH
t AC
1.5
42
60
18
18
12
2
1
2
1
ENABLE AUTO PRECHARGE
-6
120,000
MAX
COLUMN b
(A0 - A7)
D
BANK 1
T6
OUT
READ
1
m + 2
t OH
t AC
2
CAS Latency - BANK 1
MIN
1.5
42
70
20
21
14
2
1
2
1
-7
t RP - BANK 0
120,000
D
MAX
T7
OUT
NOP
m + 3
t OH
t AC
16Mb: x16
MIN
IT SDRAM
1.5
48
80
24
24
16
2
1
2
1
©1999, Micron Technology, Inc.
-8A
BANK 0
T8
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED
120,000
D
MAX
OUT
t RCD - BANK 0
t OH
t AC
b
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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