mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 48

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
CKH
CKS
CMH
A0-A9
DQM
CLK
CKE
A10
DQ
BA
3
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Faster frequencies will require two clocks (when
t CMS
t CKS
t AS
t AS
t AS
2.5
2.5
20
ACTIVE
BANK 0
1
2
6
8
1
2
1
T0
ROW
ROW
t CMH
t CKH
t AH
t AH
t AH
-6
MAX
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
MIN
T1
2.75
2.75
NOP
10
25
1
2
7
1
2
1
-7
ENABLE AUTO PRECHARGE
MAX
ALTERNATING BANK WRITE ACCESSES
t CMS
t CL
t DS
COLUMN m
(A0 - A7)
BANK 0
WRITE
T2
D
IN
MIN
t CMH
t CH
13
25
t DH
m
1
2
3
3
8
1
2
1
2
-8A
MAX
t DS
D
IN
T3
NOP
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WR >
t DS
48
D
BANK 1
ACTIVE
IN
T4
ROW
ROW
t
CK).
m + 2
t DH
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
RRD
WR
t RCD - BANK 1
t DS
D
IN
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
m + 3
t WR - BANK 0
1 + 4ns
t DH
42
60
18
18
12
2
1
2
ENABLE AUTO PRECHARGE
-6
120,000
MAX
t DS
COLUMN b
(A0 - A7)
BANK 1
WRITE
4
T6
D
IN
1
t DH
b
1 + 3ns
2
MIN
42
70
20
21
14
2
1
2
-7
t DS
120,000
t RP - BANK 0
MAX
D
NOP
T7
IN
b + 1
t DH
16Mb: x16
1 + 2ns
MIN
IT SDRAM
48
80
24
24
16
2
1
2
©1999, Micron Technology, Inc.
t DS
-8A
ACTIVE
D
BANK 0
T8
ROW
120,000
ROW
IN
MAX
b + 2
t RCD - BANK 0
DON’T CARE
UNDEFINED
t DH
UNITS
t
ns
ns
ns
ns
ns
ns
ns
ns
CK