mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 8

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

CAS Latency
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to 1, 2 or 3 clocks.
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result
of the clock edge one cycle earlier (n + m - 1), and
provided that the relevant access times are met, the
data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is
registered at T0, and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
CLK
CLK
CLK
DQ
DQ
DQ
READ
READ
READ
T0
T0
T0
CAS Latency = 1
t
t AC
LZ
CAS Latency = 2
CAS Latency
Figure 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
D
t OH
OUT
T2
NOP
T2
NOP
T2
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
8
will be valid by T2, as shown in Figure 2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
SPEED
-8A
Reserved states should not be used, as unknown
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 1
≤ 50
≤ 40
≤ 40
CAS
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
Table 2
LATENCY = 2 LATENCY = 3
≤ 125
≤ 100
≤ 77
CAS
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.
≤ 166
≤ 143
≤ 125
CAS