mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 21

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied
coincident with the BURST TERMINATE command
will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data
applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 19, where data n is
the last desired data element of a longer burst.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
Fixed-length or full-page WRITE bursts can be trun-
COMMAND
A0-A9
Terminating a WRITE Burst
CAS#
RAS#
WE#
ADDRESS
A10
CKE
NOTE: DQMs are low
CLK
CS#
BA
PRECHARGE Command
CLK
DQ
HIGH
BANK,
WRITE
COL n
DIN
T0
Figure 19
Figure 20
n
TERMINATE
BURST
BANK 0 and 1
T1
BANK 0 or 1
BANK 1
BANK 0
Command
(Address)
(Data)
Next
T2
21
PRECHARGE
the open row in a particular bank or the open row in
all banks (see Figure 20). The bank(s) will be available
for a subsequent row access some specified time (
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, input BA selects the bank. When all
banks are to be precharged, input BA is treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
POWER-DOWN
coincident with a NOP or COMMAND INHIBIT, when
no accesses are in progress (see Figure 21). If POWER-
DOWN occurs when all banks are idle, this mode is
referred to as precharge power-down; if power-down
occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering
power-down deactivates the input and output buff-
ers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-
down state longer than the refresh period (64ms) since
no refresh operations are performed in this mode.
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
COMMAND
CKE
CLK
All banks idle
The PRECHARGE command is used to deactivate
POWER-DOWN occurs if CKE is registered LOW
The power-down state is exited by registering a NOP
Enter POWER-
DOWN mode
t CKS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
Input buffers gated off
POWER-DOWN
t
Figure 21
CKS).
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
Exit POWER-
DOWN mode
< t CKS
16Mb: x16
IT SDRAM
NOP
©1999, Micron Technology, Inc.
DON’T CARE
ACTIVE
t
t RCD
t RAS
t RC
RP)