mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 5

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

PIN DESCRIPTIONS
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
11, 12, 39, 40, 42,
43, 45, 46, 48, 49
PIN NUMBERS
21-24, 27-32, 20
2, 3, 5, 6, 8, 9,
7, 13, 38, 44
4, 10, 41, 47
15, 16, 17
33, 37
26, 50
14, 36
1, 25
35
34
18
19
WE#, CAS#,
SYMBOL
A0-A10
DQML,
DQMH
DQ15
DQ0-
RAS#
V
V
CLK
CKE
CS#
V
BA
NC
V
DD
SS
DD
SS
Q
Q
Output
Supply DQ Power: Provide isolated power to DQs for improved noise immu-
Supply DQ Ground: Provide isolated ground to DQs for improved noise
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Input/ Data I/Os: Data bus.
TYPE
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
Input Chip Select: CS# enables (registered LOW) and disables (registered
Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
Input Input/Output Mask: DQM is an input mask signal for write accesses and an
Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ,
Input Address Inputs: A0-A10 are sampled during the ACTIVE command
–
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN
(row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access
in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
command being entered.
output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH
corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
WRITE or PRECHARGE command is being applied. BA is also used to
program the twelfth bit of the Mode Register.
(row-address A0-A10) and READ/WRITE command (column-address A0-
A7, with A10 defining AUTO PRECHARGE) to select one location out of
the 512K available in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
No Connect: These pins should be left unconnected.
nity.
immunity.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.