mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 34

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mt48lc1m16a1

Manufacturer Part Number
mt48lc1m16a1
Description
Synchronous Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
ADDRESS
SYMBOL* MIN
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
CKH
DQM
CKE
CLK
DQ
1
2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
3. Outputs are guaranteed High-Z after command is issued.
t CKS
(
(
(
(
(
)
)
)
)
)
(
(
(
(
(
)
Power-up:
V
CLK stable.
)
)
)
)
T=100µs
(
(
(
(
(
)
(
(
)
(
)
(
)
(
)
)
2.5
2.5
)
)
)
)
20
(MIN)
DD
1
2
6
8
1
T0
NOP
t CKH
t CMH
High-Z
and
-6
t CK
MAX
PRECHARGE
BANK(S)
MIN
2.75
2.75
T1
10
25
1
2
7
1
t CMS
t RP
Precharge
all banks.
-7
(
(
(
(
(
MAX
(
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
(
(
(
(
(
)
)
)
)
)
(
(
(
(
(
(
)
)
)
)
)
)
INITIALIZE AND LOAD MODE REGISTER
Tn + 1
REFRESH
AUTO
MIN
13
25
1
2
3
3
8
1
t CH
AUTO REFRESH
-8A
t RCAR
MAX
NOP
(
(
(
(
(
)
(
(
)
(
)
(
)
)
)
)
)
)
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
UNITS
NOP
ns
ns
ns
ns
ns
ns
ns
ns
t CL
34
To + 1
REFRESH
AUTO
AUTO REFRESH
SYMBOL* MIN
t
t
t
t
t
t
t
CKS
CMH
CMS
MRD
RC
RCAR
RP
t RC
NOP
(
(
(
(
(
(
)
)
(
)
(
)
(
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
)
)
)
)
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
NOP
60
66
18
2
1
2
2
-6
MAX
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
t AH
Program Mode Register.
MIN
70
70
21
2
1
2
2
-7
t MRD
MAX
Tp + 2
NOP
16Mb: x16
MIN
IT SDRAM
80
80
24
2
1
2
2
©1999, Micron Technology, Inc.
-8A
Tp + 3
MAX
ACTIVE
BANK,
ROW
DON’T CARE
UNDEFINED
2, 3
UNITS
t
ns
ns
ns
ns
ns
ns
CK

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