mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 41

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mt48lc1m16a1

Manufacturer Part Number
mt48lc1m16a1
Description
Synchronous Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AC (1)
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
CKH
CKS
DQM
A0-A9
CLK
CKE
A10
DQ
BA
3
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
t CMS
t CKS
t AS
t AS
t AS
2.5
2.5
ACTIVE
20
1
2
6
8
1
2
ROW
ROW
BANK
T0
t CMH
t CKH
t AH
t AH
t AH
-6
MAX
t RCD
t RAS
t RC
5.5
18
8
t CK
T1
MIN
2.75
2.75
NOP
10
25
1
2
7
1
2
ENABLE AUTO PRECHARGE
-7
MAX
5.5
8.5
22
t CMS
t CL
COLUMN m
(A0 - A7)
BANK
T2
READ
READ – WITH AUTO PRECHARGE
t CMH
MIN
t CH
13
25
1
2
3
3
8
1
2
2
CAS Latency
-8A
MAX
22
6
9
T3
NOP
t LZ
UNITS
t AC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41
T4
NOP
D
OUT
t OH
t AC
m
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
HZ (1)
LZ
OH
RAS
RC
RCD
RP
D
OUT
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
m + 1
t OH
t AC
1.5
42
60
18
18
1
2
1
-6
120,000
MAX
1
5.5
D
18
6
OUT
T6
NOP
m + 2
t OH
t AC
t RP
MIN
1.5
42
70
20
21
1
2
1
-7
120,000
D
MAX
T7
NOP
OUT
5.5
8.5
22
m + 3
t OH
t HZ
16Mb: x16
MIN
IT SDRAM
1.5
48
80
24
24
1
2
1
©1999, Micron Technology, Inc.
-8A
ACTIVE
BANK
ROW
T8
ROW
DON’T CARE
UNDEFINED
120,000
MAX
22
6
9
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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