mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 19

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

WRITEs
mand, as shown in Figure 13.
vided with the WRITE command and AUTO
PRECHARGE is either enabled or disabled for that
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic WRITE commands used in the follow-
ing illustrations, AUTO PRECHARGE is disabled.
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z, and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page it will wrap to column 0 and
continue.)
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a subsequent WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
WRITE bursts are initiated with a WRITE com-
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in element
Data for any WRITE burst may be truncated with a
A0-A7
A8-A9
CAS#
RAS#
WE#
A10
CLK
CKE
CS#
BA
WRITE Command
HIGH
Figure 13
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BANK 0
COLUMN
ADDRESS
BANK 1
19
coincident with the new command applies to the new
command. An example is shown in Figure 15. Data n
+ 1 is either the last of a burst of two, or the last desired
of a longer burst. The 1 Meg x 16 SDRAM uses a
pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture. A
WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full-speed,
random write accesses within a page can be performed
as shown in Figure 16.
COMMAND
COMMAND
ADDRESS
NOTE:
ADDRESS
CLK
DQ
NOTE:
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CLK
DQ
Burst length = 2. DQM is LOW.
WRITE
BANK,
COL n
WRITE to WRITE
T0
D
n
IN
WRITE Burst
DQM is LOW. Each WRITE
command may be to any bank.
WRITE
BANK,
COL n
D
Figure 14
Figure 15
T0
n
IN
NOP
n + 1
T1
D
IN
n + 1
NOP
T1
D
IN
NOP
DON’T CARE
T2
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.
WRITE
BANK,
COL b
T2
D
b
IN
T3
NOP