gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 169

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

This register enables/disables the pull-up resistors. If bit with 0 indicates the pull-up resistor is on.
15.20 Interrupt Enable Register (IE)
Bit No.
A8h
Symbol
EADC
ET2
ES0
ET1
EX1
ET0
EX0
EA
MiDAS1.0 Family
R/W(0)
EA
7
Function
Global Interrupt Enable. This bit controls the global masking of all interrupts except
Power-Fail interrupt, which is enabled by the EPFI bit (WDCON.5).
0: Disable all interrupt sources. This bit overrides individual interrupt mask settings.
1: Enable all individual interrupt masks. Individual interrupts will occur if enabled.
Enable ADC Interrupt. This bit controls the masking of the ADC interrupt.
0: Disable all ADC interrupts.
1: Enable interrupt requests generated by the ADCF flag (ADCON.4)
Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
Enable Serial port Interrupt. This bit controls the masking of the serial port interrupt.
0: Disable all serial port interrupts.
1: Enable interrupt requests generated by the RI (SCON.0) or TI (SCON.1) flags
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
R/W(0)
EADC
6
R/W(0)
ET2
5
R/W(0)
Page 169 of 187
ES
4
R/W(0)
ET1
3
R/W(0)
EX1
2
R/W(0)
ET0
1
R/W(0)
EX0
0
IE