gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 55

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gc80c520a

Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
MiDAS1.0 Family
SADEN is 0, the corresponding bit in SADDR is don’t care. By only the bits in SADDR whose
corresponding bits in SADEN are 1, the given address is determined. So a user can address many slaves
flexibly without changing the slave address in SADDR.
The following example shows how to address different slaves with a given address.
Slave 1:
SADDR 1010 0100
SADEN 1111 1010
Given 1010 0X0X
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0XX1
The given addresses for slave 1 and 2 have the different LSB. For slave 1: Don’t care for Slave 1, 1 for
Slave 2. Thus to communicate only with slave 1, the master must send 0 for the LSB of address value
(1010 0000). Similarly the bit 1 is 0 for slave 1 and Don’t care for slave 2. Hence to communicate only
with slave 2, the master has to transmit 1 for the bit 1 of address value (1010 0011). If the master wishes
to communicate with both slaves simultaneously, then the LSB two bits of address must be set to ‘01’.
The bit 3 position is a don’t care for both the slaves. So the two different addresses (1010 0001 and 1010
0101) can be selected.
The master can communicate with all the slaves simultaneously with the broadcast address. This address
is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits.
In most applications, a broadcast address is FFh. In the previous example, the broadcast address is
(1111 111X) for slave 1 and (1111 1111) for slave 2.
The SADDR and SADEN are located at address A9H and B9H, respectively. By reset, these two SFRs
are initialized to 00H. The given address and broadcast address are set to XXXX XXXX (i.e. all bits are
don’t care). As a result, the master cannot communicate with the slaves selectively.
6.2.6 PWM (Pulse Width Modulator)
The MiDAS1.0 family has two channels of 8-bit pulse width modulated output channels. Their pulse width
is programmable. The pulse width is adjusted by the value of SFRs; PWM0CON and PWM1CON.
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