gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 35

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.2 LVD (Low Voltage Detector)
6.2.2.1 Power–On Reset
When power is turned on, MiDAS1.0 Family starts an automatic reset by generating a power-on reset
pulse internally. Once the supply voltage, V
restart clock generation with the external crystal. After 65,536 clock cycles, the program execution will
start at location 0000h. As a result, the device starts reliable operation in the defined state established by
the reset.
A software can find out using the Power–On Reset flag (POR in WDCON[6] or PCON[4]) that a Power–
On Reset has occurred. Since the program execution always starts at location 0000h after all kinds of
resets, software should clear the POR bit after reading it.
6.2.2.2 Power-Fail Reset
When power falls below V
condition will be maintained until power returns to the proper operating levels. When power rises above
the reset threshold (V
drop of Vcc below V
6.2.2.3 Power–Fail Interrupt
All MiDAS1.0 devices detect the fall of V
flag. As a result, the power-fail interrupt occurs if enabled To do so, they compare V
reference voltage, V
change the priority level. But it can be disabled if not needed. The level of V
sheet specifications associated with each device. The EPFI bit (WDCON[5]) enables the Power–fail
Interrupt. This interrupt is independent of the global interrupt enable (EA). The Power–fail interrupt is a
level–sensitive interrupt and its flag will be maintained ‘high’ as long as V
The related SFRs are :
EXIF[0] (BGS) : If BGS = 0, LVD block stops when a device operates in power-down mode.
Default value is 1.
MiDAS1.0 Family
RST
PFI
RST
. Among all interrupts, the Power–fail Interrupt has the highest priority. Nobody can
produces the same result with power-up.
), the device will perform the power–on reset and set the POR flag. Thus the
RST
(Power-Fail), the device will once again go into reset state. This reset
CC
CC
below V
, rises above the threshold (V
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PFI
(4.0V +/- 10%) and set up the power-fail interrupt
CC
remains below V
RST
= 2.5V), the processor will
PFI
is provided in the data
CC
with their internal
PFI
.