gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 64

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.8 Interrupt
The MiDAS1.0 family has 13 interrupt sources with a four or two priority level interrupt structure. Each
interrupt source has an individual priority bit, flag, interrupt vector and enable bit. In addition, All interrupts
can be globally enabled or disabled.
6.2.8.1 Interrupt Sources
The two external interrupts /INT0 and /INT1 can be either edge or level triggered, depending on bits IT0
and IT1 in the TCON register. The bits IE0 and IE1 in the TCON register are the interrupt request bits.
The other four external interrupts of INT2, /INT3, INT4 and /INT5 are only edge triggered. INT2 and INT4
are positive edge triggered but /INT3 and /INT5 are negative edge triggered. The negative interrupt inputs,
/INT3 and /INT5, are sampled in every machine cycle. If the sampling result is high in one cycle and low
in the next, a high to low transition is detected and the interrupt request flag IEx in TCON or EXIF is set.
Similarly, a low-to-high transition of the positive interrupt inputs is detected and the interrupt request flag
is set. Since the external interrupt inputs are sampled every machine cycle, they have to be held high or
low for at least one complete machine cycle. The IEx in TCON is cleared automatically when the service
routine is called. But, IEx in EXIF must be cleared by software. For a level triggered interrupt, the interrupt
input has to be kept low till the interrupt is serviced. The request bits, IE0 and IE1, are not cleared by the
hardware for the level triggered interrupt when the interrupt is serviced. If the interrupt input continues to
be held low even after the service routine is completed, the processor may acknowledge another interrupt
request from the same source. Note that the external interrupts, INT2 to /INT5, are edge triggered only.
The individual interrupt flag corresponding to external interrupt 2 to 5 must be cleared manually by
software.
AD_REQ
AD_END
Valid Bit
AD_EN
ADCF
Set by S/W
Set by S/W
Figure 6-31 A/D Converter Timing Diagram
Setup Time
8F
ADC
Cleared by H/W
Cleared by H/W
8
7
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6
(8F
ADC
5
) x 9 bits = 72F
88F
8F
4
ADC
ADC
3
ADC
2
Functional Description
1
0
Hold Time
8F
ADC
ADC Interrupt
Set by H/W
Set by H/W