gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 66

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gc80c520a

Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
The interrupt flags are sampled at every machine cycle. In the same machine cycle, the sampled
LVD (Power Fail)
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Hierarchy
1 (highest)
2
3
4
5
6
7
8
9
10
11
12
13
UART
INT0
INT1
INT2
INT3
INT4
INT5
WDT
ADC
IT0
IT1
1
0
1
0
RI
TI
Figure 6-33 Hierarchy of Interrupt Priority
Table 6-12 Priority Structure of Interrupts
Flag Bits
WDIF
ADCF
TF0
TF1
TF2
IE2
IE3
PFI
IE0
IE1
IE4
IE5
Sources
LVD
/INT0
TF0
/INT1
TF1
RI + TI
TF2
ADC
INT2
/INT3
INT4
/INT5
WDT
Interrupt Enable Bits
EWDT
EADC
EPFI
ET2
EX2
EX3
EX4
EX5
EX0
ET0
EX1
ET1
ES
Page 66 of 187
EA
Priority
PADCH PADC
High
PX0H
PT0H
PX1H
PT1H
PT2H
PSH
Vector Address
0033h
0003h
000Bh
0013h
001Bh
0023h
002Bh
003Bh
0043h
004Bh
0053h
005Bh
0063h
0
0
0
0
0
PWDT
Priority
PX0
PT0
PX1
PT1
PT2
PX2
PX3
PX4
PX5
PS
Low
11
11
11
11
11
11
11
01
01
01
01
01
10
10
10
10
10
10
10
00
00
00
00
00
01
01
01
01
01
01
01
00
00
00
00
00
00
00
Functional Description
Priority Level
4 levels
4 levels
4 levels
4 levels
4 levels
4 levels
4 levels
2 levels
2 levels
2 levels
2 levels
2 levels
High Priority
Low Priority
High Priority
High Priority
Low Priority
High Priority
High Priority
Interrupt
Low Priority
Interrupt
Interrupt
Vector

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