gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 65

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

The TF0 and TF1 flags generate the Timer 0 and 1 interrupts. These flags are set by the overflow in the
Timer 0 and 1. The TF0 and TF1 flags are cleared automatically by the hardware when the timer interrupt
is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and the EXF2 flags. These
flags are set by overflow or capture/reload events in the Timer 2 operation. The hardware does not clear
these flags when a Timer 2 interrupt is executed. Software has to resolve the cause of the interrupt
between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-out
is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the enable bit EIE.4 enables the
interrupt, then it will occur.
The UART can generate interrupts on reception or transmission. There are two interrupt sources from the
UART, which are obtained by the RI and TI bits in the SCON. These bits are not cleared automatically by
the hardware, and a user will have to clear these bits using software.
ADCF flag and AD_END flag are set to 1 when A/D conversion is finished. Then the ADC interrupt will be
generated if it is enabled. The ADCF flag must be cleared by software in ADC interrupt routine.
PFI flag is set when Vdd drops below V
interrupt is not disabled by EA that is a global interrupt enable bit.
Each individual interrupt can be enabled or disabled by setting or clearing a bit in the IE. IE also has a
global enable/disable bit EA that can be cleared to disable all interrupts.
6.2.8.2 Priority Level Structure
There are four or two priority levels for the interrupts. Naturally, a higher priority interrupt cannot be
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below; the
interrupts are numbered starting from the highest priority to the lowest.
MiDAS1.0 Family
Interrupt
Sources
Interrupt
Flag bits
IE0
Figure 6-32 Interrupt Vector Generation Flow
[Interrupt Vector Generation Flow]
Individual
Enable
bits
EX0
PFI
. The flag generates LVD interrupt if EPFI flag is set. This
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Enable
Global
bits
EA
Priority
PX0H
bits
PX0
Generation
Polling &
Vector
0003h
Interrupt
Vector
0003h