gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 68

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

Functional Description
minimum of five complete machine cycles between activation of an external interrupt request and the
beginning of execution of the service routine’s first instruction.
A longer response time would result if any of the three conditions are not met. If a higher or equal priority
level is already in progress, the additional wait time obviously depends on the nature of the currently
executed service routine. If the polling cycle is not in the last machine cycle of the instruction in progress,
then an additional delay is introduced. The maximum response time (if no other interrupt is in service)
occurs if the MiDAS1.0 family is performing any write to IE, IP, EIE, EIP, IPH or EXIF and then executes a
4-machine cycle instruction. From the time an interrupt source is activated, the longest reaction time is 11
machine cycles. This includes 1 machine cycle to detect the interrupt, 2 machine cycles to complete the
IE, IP, EIE, EIP, IPH or EXIF access, 4 machine cycles to complete the instruction and 4 machine cycles
to complete the hardware LCALL to the interrupt vector location.
Thus in a single-interrupt system, the interrupt response time will always be more than 5 machine cycles
and not more than 11 machine cycles. The maximum latency of 11 machine cycles is 44 clock cycles.
Note that in the standard 80C52, the maximum latency is 8 machine cycles that equals 96 clock cycles.
This is more than 50% reduction in terms of clock periods.
6.2.9 Reset Circuit
The user has several hardware related options for placing the MiDAS1.0 family into reset state. In general,
most register bits go to their reset values irrespective of the current states, but there are a few flags
whose state depends on the source of reset. The user can use these flags to find the cause of reset using
software. There are three ways of putting the device into reset state. They are Power on/fail reset,
External reset, and Watchdog reset as shown in Figure 6-34.
POR
VDD
LVD RESET
LVD
Generation
External RESET
RESET
Internal RESET
Generation
(Min. 24 Clocks Period)
WTRF
WDT
Delay
WDT RESET
Clock
27 bits Counter
512 Clocks
Generation
EWT
Initialize
Figure 6-34 Three Reset Resources
Page 68 of 187