gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 62

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

T
W
u
P
6.2.7.1 INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC block diagram (Figure 6-30), the analog input voltage is compared to the reference voltage.
The analog input voltage must be within the range from V
The resistor tree generated different reference internally during the analog-to-digital conversion process
for each conversion step. The reference voltage level for the first bit conversion is always 1/2 V
6.2.7.2 CONVERSION TIMING
The A/D conversion process requires total 88 clock cycles.
T
W
u
P
p
h
p
h
1
1
h
h
e
e
S
S
e
e
r
r
E
e
E
A
e
A
n
n
s
s
L
L
D
D
u
u
i
i
[
[
s
s
C
C
2
2
ADC0
ADC1
ADC2
ADC3
s
s
(P0.0)
(P1.1)
(P1.2)
(P1.3)
t
t
]
e
o
]
Setup time: 8 clock cycles
Conversion time: 9bit x 8 clock cycles = 72 clock cycles
Hold time: 8 clock cycles
e
o
i
i
d
r
a
d
r
a
n
n
s
s
n
n
p
p
.
f
f
.
d
o
d
u
o
u
T
T
r
r
t
t
P
P
o
o
p
p
A
A
ADC0
ADC1
ADC2
ADC3
1
1
i
i
D
D
n
n
S
S
s
s
s
s
C
w
C
w
E
E
a
a
i
L
i
L
t
i
t
i
c
r
n
c
r
n
[
[
e
3
e
3
h
p
h
p
]
]
Figure 6-30 Analog-to-Digital Converter block Diagram
u
a
u
.
a
.
o
o
t
t
l
l
t
s
s
t
Analog
f
f
e
e
f
f
MUX
,
ACH1
ACH0
,
r
r
t
t
n
t
t
n
h
h
h
h
a
a
e
e
e
e
t
t
y
y
e
e
p
p
l
l
m
y
m
y
u
u
u
u
u
l
u
l
l
l
-
s
-
s
s
s
AD_EN
u
u
e
t
e
t
p
p
d
b
d
b
Control
Circuit
e
e
r
f
r
f
o
e
e
o
c
c
r
s
r
s
o
AD_REQ
o
i
i
d
d
s
s
n
n
i
i
t
t
Page 62 of 187
g
f
f
g
(= V
o
o
i
i
AV
g
D/A Converter
i
g
i
r
r
t
t
s
s
a
u
u
a
REF
,
,
l
r
l
r
DD
e
e
i
i
s
s
n
n
)
d
d
e
e
p
p
t
a
t
a
u
u
s
s
V
t
t
t
t
h
h
SS
i
i
Analog
Comparator
a
a
n
n
e
e
SS
n
n
P
P
a
a
p
p
0
0
ADIV2
ADIV1
ADIV0
l
to V
l
u
u
o
o
[
[
l
l
0
0
g
g
l
l
-
-
]
]
u
u
,
,
i
i
DD.
n
n
p
8 7
p
P
P
p
p
1
1
u
u
c
c
[
[
t
o
t
o
1
1
.
6
.
Functional Description
n
n
]
ADCR
]
Clock prescaling
A
A
System Clock
,
,
Approximation
t
t
5
r
r
P
P
l
l
Successive
s
o
o
s
4
Register
1
1
o
o
l
l
[
[
,
,
b
3 2 1
2
2
b
y
y
]
i
]
i
t
t
,
,
o
o
s
s
F
SAR[8:0]
SAR[8:1]
a
a
u
u
ADC
:
:
n
n
s
t
s
t
d
d
h
h
h
h
e
e
P
P
o
o
u
u
1
1
P
P
l
[
l
[
d
d
0
3
3
0
]
S
]
S
s
s
.
.
ADCON
w
E
E
w
AD_END
L
L
i
i
ADCF
ADC Interrupt Flag
t
t
c
[
c
[
0
0
h
h
SAR[0]
]
]
,
,
o
o
DD.
P
f
P
f
f
f
1
1
t
t
0
h
h
S
S
e
e
E
E
L
p
L
p
[
u
[
u
1
1
l
l
l
]
l
]
-
-
,
,