gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 39

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

The Watchdog timer will be disabled by a power-on/fail reset. The Watchdog timer reset does not disable
the watchdog timer, but will restart it. In general, software should restart the timer to put it into a known
state.
The default Watchdog time-out interval is 2
6.2.4 Timer 0/1/2
The MiDAS1.0 family has three 16-bit programmable timer/counters.
6.2.4.1 Timer/Counters 0 & 1
Each of these Timer/Counters has two 8-bit registers that form the 16-bit counting register. For
Timer/Counter 0, they are the upper 8-bit register TH0 and the lower 8-bit register TL0. Similarly,
Timer/Counter 1 has two 8-bit registers, TH1 and TL1. They can be configured to operate either as timers
or event counters.
When operating as a timer, the counting registers counts clock cycles. The timer clock frequency can be
1/12 or 1/4 of the system clock frequency. In the “Counter” function, the register is incremented in
response to a 1-to-0 transition at its corresponding external input pin, T0 pin for Timer 0 and T1 pin for
Timer 1. The T0 and T1 external inputs are sampled during S3 state of every 4-clock system or every 12-
clock system. If the sampled value is high in one machine cycle and low in the next, a valid high-to-low
transition on the pin is recognized and the count register is incremented. Since it takes 8 clocks (4-clock
system) or 24 clocks (12-clock system) to recognize a negative transition on the pin, the maximum
counting rate is 1/8 or 1/24 of the master clock frequency. In either the “Timer” or “Counter” mode, the
count register will be updated at S2 state. Therefore, in the “Counter” mode, the recognized negative
transition on T0 or T1 pin causes the counting register value to increase in the next machine cycle after
the negative edge was detected.
WD1
0
0
1
1
MiDAS1.0 Family
WD0
0
1
0
1
2
2
2
2
17
20
23
26
Interrupt time-out (@25MHz)
clocks
clocks
clocks
clocks
Table 6-6 Time-out values for the Watchdog timer
17
clocks, which is the shortest time-out period.
Page 39 of 187
2684.35ms
335.54ms
41.94ms
5.24ms
2
2
2
2
17
20
23
26
+ 512 clocks
+ 512 clocks
+ 512 clocks
+ 512 clocks
Reset time-out (@25MHz)
2684.38ms
335.56ms
41.96ms
5.26ms