gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 40

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

Functional Description
The “Timer” or “Counter” mode is selected by the control bit “C/T” in the TMOD SFR; bit 2 of TMOD
selects the mode for Timer/Counter 0 and bit 6 of TMOD the mode for Timer/Counter 1. In addition, each
Timer/Counter has four operating modes. The modes are selected by bits M0 and M1 in the TMOD SFR.
6.2.4.1.1 Time-base Selection
The MiDAS1.0 family provides the two time-bases for the timer/counter. Its timers can operate at the
same speed with those of the standard 80C52 family, counting at the rate of 1/12 of the clock speed. This
can ensure that timer programs of the MiDAS1.0 family have the same timing with those of the standard
80C52 family. This is the default time-base of the GC80C520 timers. However, the timers of the
MiDAS1.0 family can also operate in the turbo mode, where they increments at the rate of 1/4 clock
speed. This mode is selected by the T0M and T1M bits in CKCON SFR. A reset clears these bits to 0,
and the timers then operate in the standard 80C52 mode. The user should set these bits to 1 if the timers
are to operate in turbo mode.
6.2.4.1.2 Mode 0
In Mode 0, the timer/counters operate as an 8-bit counter with a divide-by-32 prescaler. This 13-bit
counter consists of 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate
and should be ignored.
The value in the TLx register increases at the negative edge of the clock. Every time the value of the fifth
bit in TLx changes from 1 to 0, the count in the THx register increases. When the count in THx rolls over
from FFh to 00h, the overflow flag TFx in TCON SFR is set. The counted input is enabled only if TRx is
set and either GATE=0 or /INTx=1. When C/T is cleared to 0, it will count clock cycles, and if C/T is set to
1, then it will count 1 to 0 transitions on T0 (P3.4) for Timer 0 and T1 (P3.5) for Timer 1.
When the 13-bit counter rolls over from 1FFFh to 000H, the timer overflow flag TFx of the relevant timer is
set. If enabled, a timer interrupt will occur. When used as a timer, the time-base is selected as either
{clock cycles/12} or {clock cycles/4} by the bits TxM of the CKCON SFR.
6.2.4.1.3 Mode 1
Mode 1 is the same as Mode 0, except that the timer register is being run with all 16 bits counter. This
means that all the bits of THx and TLx are used. Roll-over occurs when the timer changes from FFFFh to
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