dp83251 National Semiconductor Corporation, dp83251 Datasheet
dp83251
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dp83251 Summary of contents
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... DP83251 55 PLAYER (FDDI Physical Layer Controller) General Description The DP83251 DP83255 PLAYER device implements one Physical Layer (PHY) entity as defined by the Fiber Distribut- ed Data Interface (FDDI) ANSI X3T9 5 Standard The PLAY- ER device contains NRZ NRZI and 4B 5B encoders and decoders serializer deserializer framing logic elasticity ...
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... MODES OF OPERATION 4 1 Run Mode 4 2 Stop Mode 4 3 Loopback Mode 4 4 Cascade Mode 5 0 REGISTERS 6 0 PIN DESCRIPTIONS 6 1 DP83251 6 2 DP83255 Table of Contents 7 0 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings 7 2 Recommended Operating Conditions Electrical Charcteristics Electrical Charcteristics ...
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... Clock Distribution Device From MHz reference the Clock Distribution Device synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks required by the BSI BMAC and PLAYER devices DP83251 55 PLAYER Device TM Physical Layer Controller The PLAYER device implements the Physical Layer (PHY) ...
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Architecture Description 2 1 OVERVIEW The PLAYER device is comprised of four blocks Receiver Transmitter Configuration Switch and Control Bus Interface as shown in Figure 2-1 Receiver During normal operation the Receiver Block accepts serial data as inputs ...
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... Each byte-wide interface consists of a parity bit (odd parity) a control bit and two 4-bit symbols The DP8355 PLAYER device has two PHY Port Interfaces and the DP83251 has only one PHY Port Interface Control Bus Interface The Control Bus Interface connects the PLAYER device to ...
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Functional Description NRZI TO NRZ DECODER The NRZI to NRZ Decoder converts Non-Return-To-Zero- Invert-On-Ones data to Non-Return-To-Zero data This function can be enabled and disabled through bit 7 (RNRZ) of the Mode Register (MR) When the bit is ...
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Functional Description No Signal Detect The Line State Detector recognizes the incoming data the No Signal Detect state upon the deassertion of the Signal Detect signal No Signal Detect indicates that the incoming link is ...
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Functional Description 3 2 TRANSMITTER BLOCK The Transmitter Block accepts 10-bit bytes from the Config- uration Switch The Transmitter Block performs the following operations Encodes the data from coding Filters out code violations ...
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Functional Description DATA REGISTERS Data from the Configuration Switch is stored in the Data Registers The 10-bit byte-wide data consists of a parity bit a control bit and two 4-bit symbols as shown in Figure 3 ...
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Functional Description INJECTION CONTROL LOGIC The Injection Control Logic replaces the data stream with a programmable symbol pair This function is used to transmit data other than the normal data frame or Line States The Injection Symbols overwrite ...
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... PHY Port interface (see Figure The DP83251 having only one port interface uses the B Request and A Indicate paths as its external port The A Request and B Indicate paths of the DP83251 are null connections and are not used by this device (see Figure 10386 – ...
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... The Single Attach Station can be connected to either the Primary or Secondary ring via a Concentrator Only 1 MAC is needed in a SAS Both the DP83251 and DP83255 can be used in a Single Attach Station The DP83251 can be connected to the MAC via its only PHY Port Interface The DP83255 can be con- ...
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... Using the PLAYER devices a Concentrator can be built with many different configurations without the need of any exter- nal logic Both the DP83251 and DP83255 can be used to build a Single Attach Concentrator Only the DP83255 is recom- mended for the Dual Attach Concentrator design See Application Note 675 Designing FDDI Concentrators ...
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Functional Description FIGURE 3-10 Single Attach Concentrator (SAC) Single MAC FIGURE 3-11 Dual Attach Concentrator (DAC) Single MAC FIGURE 3-12 Dual Attach Concentrator (DAC) Dual MACs (Continued 10386 – 10386 – 13 ...
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... The PLAYER device operates in the STOP mode while it is being initialized or configured The PLAYER device is also reset to the STOP mode auto- matically when the RST pin (pin 71 on the DP83251 and pin 111 on the DP83255) is set to ground When in STOP mode the PLAYER device performs the fol- ...
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Modes of Operation (Continued Internal Loopback The Internal Loopback mode can be used to test the func- tionality of the PLAYER device and to test the data paths between the PLAYER and BMAC devices before ...
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Modes of Operation (Continued External Loopback The External Loopback mode can be used to test the func- tionality of the PLAYER device and to test the data paths between the PLAYER CRD and BMAC devices ...
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Modes of Operation (Continued CASCADE MODE The PLAYER device can operate in the Cascade (parallel) mode Figure 4-4 which is used in high bandwidth point- to-point data transfer applications This is a non-FDDI mode of operation ...
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Modes of Operation (Continued) FIGURE 4-5 Cascade Mode of Operation Note N is recommended to be less than 3 for this mode See Application Note 679 for larger values of N FIGURE 4-4 Parallel Transmission ...
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Registers The PLAYER device is initialized configured and monitored via 32 8-bit registers These registers are accessible through the Control Bus Interface Table 5 Register Summary List Table 5-2 shows the contents of each register Register ...
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Registers (Continued) TABLE 5-2 Register Content Summary Register Register Address Symbol D7 00h MR RNRZ TNRZ 01h CR BIE AIE 02h ICR UDI RCB 03h ICMR UDIM RCBM 04h CTSR RES PRDPE 05h IJTR IJT7 IJT6 06h ISRA ...
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Registers (Continued) MODE REGISTER (MR) The Mode Register is used to initialize and configure the PLAYER device In order to minimize interruptions on the network it is recommended that the PLAYER device first be put in STOP mode ...
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... The Configuration Register controls the Configuration Switch Block and enables disables both the A and B Indicate output ports Note that the B Indicate output port is offered only on the DP83255 (for Dual Attach Stations) and not in the DP83251 (for Single Attach Stations) For further information refer to Section 3 3 Configuration Switch ...
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Registers (Continued) INTERRUPT CONDITION REGISTER (ICR) The Interrupt Condition Register records the occurrence of an internal error event the detection of Line State an unsuccessful write by the Control Bus Interface the expiration of an internal counter or ...
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Registers (Continued) INTERRUPT CONDITION REGISTER (ICR) (Continued) Bit Symbol D4 LEMT LINK ERROR MONITOR THRESHOLD This bit is set to 1 when the internal 8-bit Link Error Monitor Counter reaches zero It will remain set until cleared by ...
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Registers (Continued) INTERRUPT CONDITION MASK REGISTER (ICMR) The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt e The Interrupt pin will be asserted (i e INT 1 and the corresponding ...
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Registers (Continued) CURRENT TRANSMIT STATE REGISTER (CTSR) The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle Master Halt Quiet or user programmable symbol pairs in addition to the normal transmission of ...
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Registers (Continued) CURRENT TRANSMIT STATE REGISTER (CTSR) (Continued) Bit Symbol D3 D4 IC0 IC1 Injection Control overwrite data from the Smoother Repeat Filter Encoder and Transmit Modes IC0 is the only bit of the register that is automatically ...
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Registers (Continued) INJECTION THRESHOLD REGISTER (IJTR) The Injection Threshold Register in conjunction with the Injection Control bits (IC (CTSR) set the frequency at which the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are inserted ...
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Registers (Continued) INJECTION SYMBOL REGISTER A (ISRA) The Injection Symbol Register A along with Injection Symbol Register B contains the programmable value (already in 5B code) that will replace the data symbol pairs The One Shot mode ISRA ...
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Registers (Continued) INJECTION SYMBOL REGISTER B (ISRB) The Injection Symbol Register B along with Injection Symbol Register A contains the programmable value (already in 5B code) that will replace the data symbol pairs The One Shot mode ISRA ...
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Registers (Continued) CURRENT RECEIVE STATE REGISTER (CRSR) The Current Receive State Register represents the current line state being detected by the Receiver Block Once the Receiver Block recognizes a new Line State the bits corresponding to the previous ...
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Registers (Continued) CURRENT RECEIVE STATE REGISTER (CRSR) (Continued) Bit Symbol D5 RES RESERVED Reserved for future use The reserved bit is set to 0 Note Users are discouraged from using this bit An attempt to write into this ...
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Registers (Continued) RECEIVE CONDITION REGISTER A (RCRA) The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block When a new Line State is entered the bit corresponding to that line ...
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Registers (Continued) RECEIVE CONDITION REGISTER B (RCRB) The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block When a new Line State is entered the bit corresponding to that line ...
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Registers (Continued) RECEIVE CONDITION MASK REGISTER A (RCMRA) The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) ...
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Registers (Continued) RECEIVE CONDITION MASK REGISTER B (RCMRB) The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt The Receiver Condition B bit (RCB) of the Interrupt Condition Register (ICR) ...
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Registers (Continued) NOISE THRESHOLD REGISTER (NTR) The Noise Threshold Register contains the start value for the Noise Counter This counter may be used in conjunction with the Noise Prescale Counter for counting the Noise events Definiton of Noise ...
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Registers (Continued) NOISE PRESCALE THRESHOLD REGISTER (NPTR) The Noise Prescale Threshold Register contains the start value for the Noise Prescale Counter The Noise Prescale Counter is a count-down counter and it is used in conjunction with the Noise ...
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Registers (Continued) CURRENT NOISE COUNT REGISTER (CNCR) The Current Noise Count Register takes a snap-shot of the Noise Counter during every Control Bus Interface read-cycle of this register During a Control Bus Interface write-cycle to the Current Noise ...
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Registers (Continued) CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR) The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Counter during every Control Bus Interface read-cycle of this register During a Control Bus Interface write-cycle to ...
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Registers (Continued) STATE THRESHOLD REGISTER (STR) The State Threshold Register contains the start value of the State Counter This counter is used in conjunction with the State Prescale Counter to count the Line State duration The State Counter ...
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Registers (Continued) STATE PRESCALE THRESHOLD REGISTER (SPTR) The State Prescale Threshold Register contains the start value for the State Prescale Counter The State Prescale Counter is a down counter The Register is used in conjunction with the State ...
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Registers (Continued) CURRENT STATE COUNT REGISTER (CSCR) The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read-cycle of this register During a Control Bus Interface write-cycle to the Current State ...
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Registers (Continued) CURRENT STATE PRESCALE COUNT REGISTER (CSPCR) The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus interface read-cycle of this register During a Control Bus Interface write-cycle to ...
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Registers (Continued) LINK ERROR THRESHOLD REGISTER (LETR) The Link Error Threshold Register contains the start value for the Link Error Monitor Counter which is an 8-bit down-counter that decrements if link errors are detected When the Counter reaches ...
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Registers (Continued) CURRENT LINK ERROR COUNT REGISTER (CLECR) The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface read-cycle of this register During a Control Bus Interface write-cycle ...
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Registers (Continued) USER DEFINABLE REGISTER (UDR) The User Definable Register is used to monitor and control events which are external to the PLAYER device The value of the Sense Bits reflects the asserted deasserted state of their corresponding ...
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Registers (Continued) DEVICE ID REGISTER (IDR) The Device ID Register contains the binary equivalent of the revision number for this device It can be used to ensure proper software and hardware versions are matched During the Control Bus ...
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Registers (Continued) CURRENT INJECTION COUNT REGISTER (CIJCR) The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read-cycle of this register During a Control Bus Interface write-cycle the PLAYER device will ...
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Registers (Continued) INTERRUPT CONDITION COMPARISON REGISTER (ICCR) The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the Control Bus Interface ...
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Registers (Continued) CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR) The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the Control ...
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Registers (Continued) RECEIVE CONDITION COMPARISON REGISTER A (RCCRA) The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the Control ...
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Registers (Continued) RECEIVE CONDITION COMPARISON REGISTER B (RCCRB) The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the Control ...
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... Pin Descriptions 6 1 DP83251 The pin descriptions for the DP83251 are divided into 5 functional interfaces Serial Interface PHY Port Interface Control Bus Interface Clock Interface and Miscellaneous Interface For a Pinout Summary List refer to Table 6-1 FIGURE 6-1 DP83251 84-Pin PLCC Pinout Order Number DP83251V ...
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... PHY Port A Indicate Data 27 PHY Port A Indicate Data 28 PHY Port A Indicate Data 29 Cascade Start 30 Cascade Ready 31 No Connect 32 No Connect 33 Clock Detect 34 Signal Detect 35 External Loopback Enable TABLE 6-1 DP83251 Pinout Summary Symbol l 2 CBD2 l 3 CBD3 GND l 4 CBD4 l 5 CBD5 ...
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... Pin Descriptions (Continued) TABLE 6-1 DP83251 Pinout Summary (Continued) Pin No Signal Name a 36 Receive Bit Clock b 37 Receive Bit Clock 38 ECL Logic Power a 39 Receive Data b 40 Receive Data 41 ECL Logic Ground 42 External Loopback Data 43 External Loopback Data 44 ECL I O Power ...
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... Pin Descriptions (Continued) TABLE 6-1 DP83251 Pinout Summary (Continued) Pin No Signal Name E PLAYER Device Reset 71 Read E Write 72 73 Chip Enable E Interrupt 74 E Acknowledge 75 76 Control Bus Address 77 Control Bus Address 78 Control Bus Address 79 Control Bus Address 80 Control Bus Address 81 CMOS Logic Power ...
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Pin Descriptions (Continued) SERIAL INTERFACE The Serial Interface consists signals used to connect the PLAYER device to the Physical Medium Dependent (PMD) sublayer The PLAYER device uses these signals to interface to a Fiber Optic ...
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... PHY PORT INTERFACE The PHY Port Interface consists signals used to connect the PLAYER Device to the Media Access Control (MAC) sublayer or other PLAYER Devices The DP83251 Device has one PHY Port Interface which consists of the B Request and the A Indicate paths Each path consists of an odd parity bit a control bit and two 4-bit symbols ...
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Pin Descriptions (Continued) CONTROL BUS INTERFACE The Control Bus Interface consists signals used to connect the PLAYER device to Station Management (SMT) The Control Bus is an asynchronous interface between the PLAYER device and a ...
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Pin Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists MHz and 125 MHz clocks used by the PLAYER device The clocks are generated by either the Clock Distribution Device or Clock Recovery Device Symbol Pin ...
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Pin Descriptions (Continued) MISCELLANOUS INTERFACE The Miscellaneous Interface consists of a reset signal user definable sense signals user definable enable signals Cascaded PLAYER devices synchronization signals ground signals and power signals Symbol Pin RST 71 ...
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Pin Descriptions (Continued) POWER AND GROUND All power pins should be connected to a single 5V power supply All ground pins should be connected to a common 0V supply Symbol Pin GND 3 Ground Power ...
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Pin Descriptions (Continued DP83255 The pin descriptions for the DP83255 are divided into six functional interfaces Serial Interface PHY Port Interface Control Bus Interface Clock Interface and Miscellaneous Interface For a Pinout Summary List refer to ...
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Pin Descriptions (Continued) Pin No Signal Name 1 CMOS Logic Ground k 2 Control Bus Data k 3 Control Bus Data 4 CMOS I O Ground k 5 Control Bus Data k 6 Control Bus Data 7 CMOS ...
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Pin Descriptions (Continued) TABLE 6-2 DP83255 Pinout Summary (Continued) Pin No Signal Name 36 PHY A Indicate Data 37 PHY A Request Data 38 CMOS Logic Ground 39 PHY Port A Indicate Data 40 PHY Port A Request ...
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Pin Descriptions (Continued) TABLE 6-2 DP83255 Pinout Summary (Continued) Pin No Signal Name 71 ECL Logic Ground a 72 Transmit Bit Clock b 73 Transmit Bit Clock 74 ECL Logic Power 75 Transmit Byte Clock 76 Transmit Byte ...
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Pin Descriptions (Continued) TABLE 6-2 DP83255 Pinout Summary (Continued) Pin No Signal Name 106 PHY Port B Request Data 107 PHY Port B Indicate Control 108 PHY Port B Request Control 109 PHY Port B Indicate Parity 110 ...
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Pin Descriptions (Continued) SERIAL INTERFACE The Serial Interface consists signals used to connect the PLAYER device to the Physical Medium Dependent (PMD) sublayer The PLAYER device uses these signals to interface to a Fiber Optic ...
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Pin Descriptions (Continued) PHY PORT INTERFACE The PHY Port Interface consists signals used to connect the PLAYER Device to the Media Access Control (MAC) sublayer or other PLAYER Devices The DP83255 Device has two PHY ...
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Pin Descriptions (Continued) PHY PORT INTERFACE (Continued) Symbol Pin BIP 109 O PHY Port B Indicate Parity A TTL output signal representing odd parity for the 10-bit wide Port B Indicate signals (BIP BIC and ...
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Pin Descriptions (Continued) CONTROL BUS INTERFACE The Control Bus Interface consists signals used to connect the PLAYER device to Station Management (SMT) The Control Bus is an asynchronous interface between the PLAYER device and a ...
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Pin Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists MHz and 125 MHz clocks used by the PLAYER device The clocks are generated by either the Clock Distribution Device or Clock Recovery Device Symbol Pin ...
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Pin Descriptions (Continued) MISCELLANEOUS INTERFACE The Miscellaneous Interface consists of a reset signal user definable sense signals user definable enable signals Cascaded PLAYER device’s synchronization signals ground signals and power signals Symbol Pin RST 111 ...
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Pin Descriptions (Continued) POWER AND GROUND All power pins should be connected to a single 5V power supply All ground pins should be connected to a common 0V ground supply Symbol Pin GND 1 Ground ...
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Pin Descriptions (Continued) NO CONNECT PINS Symbol Pin Connect Not used by the PLAYER device Connect Not used by the PLAYER device Connect ...
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Electrical Characteristics 7 1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC DC Input Voltage IN DC Output Voltage OUT Storage Temperature 7 2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter V Supply Voltage CC T Operating Temperature A ...
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Electrical Characteristics DC electrical characteristics for all Open Drain output signals (INT ACK and CR) Symbol Parameter V Output Low Voltage OL I TRI-STATE Leakage OZ DC electrical characteristics for all 100k ECL input and output signals Symbol ...
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Electrical Characteristics ELECTRICAL CHARACTERISTICS The AC Electrical characteristics are over the operating range unless otherwise specified AC Characteristics for the Control Bus Interface Symbol Parameter T1 CE Setup to LBC T2 LBC Period T3 LBC ...
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Electrical Characteristics FIGURE 7-1 Control Bus Write Cycle Timing FIGURE 7-3 Control Bus Synchronous Write Cycle Timing FIGURE 7-4 Control Bus Synchronous Read Cycle Timing FIGURE 7-5 Control Bus Interrupt Timing (Continued 10386 – 22 FIGURE ...
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Electrical Characteristics AC Characteristics for the Clock Signals Symbol Parameter T23 TBC to TXC Hold Time T24 TBC to TXC Setup Time T25 TBC to LBC Skew T26 RXC Duty Cycle T27 TXC Duty Cycle T28 TBC Duty ...
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Electrical Characteristics AC Characteristics for PHY Port Interfaces Symbol Parameter T30 LBC to Indicate Data Changes from TRI-STATE to Data Valid T31 LBC to Indicate Data Changes from Active to TRI-STATE T32 LBC to Indicate Data Sustain T33 ...
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Electrical Characteristics AC Characteristics for the Serial Interface Symbol Parameter T36 RXD to RXC Setup Time T37 RXD to RXC Hold Time T38 TXC to TXD Change Time T39 TXC to LBD Change Time T40 CD Min Pulse ...
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Electrical Characteristics TEST CIRCUITS Note S is closed for T and T 1 PZL PLZ S is closed for T and T 2 PZH PHZ S and S are open otherwise 1 2 FIGURE 7-9 ...
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Test Waveforms FIGURE 7-13 ECL Output Test Waveform Note All CMOS inputs and outputs are TTL compatible FIGURE 7-14 TTL Output Test Waveform FIGURE 7-15 TRI-STATE Output Test Waveform TL F 10386 – 10386 – ...
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Detailed Descriptions This section describes in detail several functions that had been discussed previously in Section 3 0 Functional De- scriptions 8 1 FRAMING HOLD RULES DETECTING JK The JK symbol pair can be used to detect the ...
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Detailed Descriptions (Continued LINK ERRORS A Link Error is defined as follows Link Error Event ALS ALS E ( JK) ...
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Detailed Description (Continued REPEAT FILTER The repeat filter prevents the propagation of code violations to the downstream station Note Inputs to the Repeat Filter state machine are shown above the transition lines while outputs from the ...
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Detailed Descriptions (Continued) TABLE 8-1 Abreviations used in the Repeat Filter State Diagram F IDLE Force Idle True when not in Active Transmit Mode W Represents the symbols TPARITY Parity error e ...
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Detailed Descriptions (Continued SMOOTHER Notes SE Smoother Enable C Preamble Counter F IDLE Force Idle (Stop or ATM) X Current Byte n X Previous Byte RST FIGURE 8-2 Smoother State Diagram 91 ...
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Detailed Descriptions (Continued NATIONAL BYTE-WIDE CODE FOR PHY-MAC IN- TERFACE The PLAYER device outputs the National byte-wide code from its PHY Port Indicate Output to the MAC device Each National byte-wide code may contain data or ...
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Detailed Descriptions (Continued) Symbol 1 Current Line State Control Bit ALS 0 ALS 0 ALS 1 ALS 1 ILS 1 ILS 1 ILS x ILS x Stuff Byte during ILS x Not ALS and Not ILS 1 Not ...
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Detailed Descriptions (Continued) Example Incoming 5B Code 98765 43210 11111 11111 (II) 11111 11111 (II) 11111 11111 (II) 11000 10001 (JK (xx ...
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... Physical Dimensions inches (millimeters) Plastic Leaded Chip Carrier Order Number DP83251V NS Package Number V84A 95 ...
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Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 ...