dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 29
dp83251
Manufacturer Part Number
dp83251
Description
Player Device Fddi Physical Layer Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83251.pdf
(96 pages)
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5 0 Registers
INJECTION THRESHOLD REGISTER (IJTR)
The Injection Threshold Register in conjunction with the Injection Control bits (IC
(CTSR) set the frequency at which the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are inserted
into the data stream It contains the start value for the Injection Counter
The Injection Threshold Register value is loaded into the Injection Counter when the counter reaches zero or during every
Control Bus Interface write-cycle of this register
The Injection Counter is an 8-bit down-counter which decrements every 80 ns Its current value is read for CIJCR
The counter is active only during One Shot or Periodic Injection Modes (i e Injection Control
Current Transmit State Register (CTSR) are set to either 01 or 10) The Transmitter Block will replace a data symbol pair with
ISRA and ISRB when the counter reaches 0 and the Injection Mode is either One Shot or Periodic
If the Injection Threshold Register is set to 0 during the One Shot mode the JK will be replaced with ISRA and ISRB If the
Injection Threshold Register is set to 0 during the Periodic mode all data symbols are replaced with ISRA and ISRB
The counter is initialized to 0 during the reset process (i e RST
For further information see the Injection Control Logic subsection within Section 3 2
ACCESS RULES
D0
D1 – 6
D7
D7
IJT7
ADDRESS
Bit
05h
D6
IJT6
(Continued)
IJT0
IJT1 – 6
IJT7
Symbol
READ
Always
D5
IJT5
D4
IJT4
INJECTION THRESHOLD BIT
value for the Injection Counter
INJECTION THRESHOLD BIT
Injection Counter
INJECTION THRESHOLD BIT
value for the Injection Counter
WRITE
Always
D3
IJT3
29
e
GND)
D2
IJT2
k
k
k
0
1 – 6
7
Description
l
l
k
l
Least significant bit (LSB) of the start
Most significant bit (MSB) of the start
1 0
D1
IJT1
Intermediate bits of start value for the
l
) in the Current Transmit State Register
k
D0
IJT0
1 0
l
bits (IC
k
1 0
l
) of the
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