dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 6

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

3 0 Functional Description
NRZI TO NRZ DECODER
The NRZI to NRZ Decoder converts Non-Return-To-Zero-
Invert-On-Ones data to Non-Return-To-Zero data
This function can be enabled and disabled through bit 7
(RNRZ) of the Mode Register (MR) When the bit is cleared
it converts the incoming bit stream from NRZI to NRZ
When the bit is set the incoming NRZ bit stream is passed
unchanged
SHIFT REGISTER
The Shift Register converts the serial bit stream into sym-
bol-wide data for the 5B 4B Decoder
The Shift Register also provides byte-wide data for the
Framing Logic
FRAMING LOGIC
The Framing Logic performs the Framing function by detect-
ing the beginning of a frame or the Halt-Halt or Halt-Quiet
symbol pair
The J-K symbol pair (11000 10001) indicates the beginning
of a frame during normal operation The Halt-Halt (00100
00100) and Halt-Quiet (00100 00000) symbol pairs are de-
tected during Connection Management (CMT)
Framing can be temporarily suspended (i e framing hold) in
order to maintain data integrity The Framing Hold rules are
explained in Section 8 1
SYMBOL DECODER
The Symbol Decoder is a two level system The first level is
a 5-bit to 4-bit converter and the second level is a 4-bit
symbol pair to the NSC byte-wide code converter
The first level latches the received 5-bit symbols and de-
codes them into 4-bit symbols Symbols are decoded into
two types data and control The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder See Table 3-1 for the 5B 4B Symbol Decoding
list
The second level translates two 4-bit symbols from the 5B
4B converter and the line state information from the Line
State Detector into the National byte-wide code More de-
tails on the National byte-wide code can be found in Section
8 6
LINE STATE DETECTOR
The FDDI Physical Layer (PHY) standard specifies eight
Line States that the Physical Layer can transmit These Line
States are used in the Connection Management process
They are also used to indicate data within a frame during the
normal operation
The Line State Detector detects nine Line States one more
than the required Line States specified in the standard
The Line States are reported through the Current Receive
State Register (CRSR) Receive Condition Register A
(RCRA) and Receive Condition Register B (RCRB)
Line States Description
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair)
The Line State Detector continues to indicate Active Line
State while receiving data symbols Ending Delimiter (T
symbols) and Frame Status symbols (R and S) after the JK
symbol pair
(Continued)
6
Idle Line State
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases)
Idle Line State indicates the preamble of a frame or the lack
for frame transmission during normal operation Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process
Notes
V denotes PHY Invalid or an Elasticity Buffer stuff byte
I denotes Idle symbol in ILS or an Elasticity Buffer stuff byte
Super Idle Line State
The Line State Detector recognizes the incoming data to be
in the Super Idle Line State upon the reception of eight con-
secutive Idle symbol pairs nominally (plus 1 symbol pair)
The Super Idle Line State is used to insure synchronization
I (Idle)
H (Halt)
JK (Starting
T (Ending
R (Reset)
S (Set)
Q (Quiet)
V (Violation)
V
V
V
V
V
V
V
V
I
Symbol
Delimiter)
Delimiter)
A
B
C
D
E
0
1
2
3
4
5
6
7
8
9
F
TABLE 3-1 Symbol Decoding
Incoming 5B
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
00100
11000
10001
01101
00111
11001
00000
00001
00010
00011
00101
00110
01000
01100
10000
Decoded 4B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1010
0001
1101
0101
0110
0111
0010
0010
0010
0010
0010
0010
0010
0010
0010
0011
1011