dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 26

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
INTERRUPT CONDITION MASK REGISTER (ICMR)
The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt
The Interrupt pin will be asserted (i e INT
1 and the corresponding mask bits in this register are also set to 1
This register is cleared (i e set to 0) and all interrupts are initially masked during the reset process
ACCESS RULES
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D7
UDIM
ADDRESS
03h
Symbol
DPEM
CPEM
CCRM
CWIM
LEMTM
RCAM
RCBM
UDIM
D6
RCBM
(Continued)
PHY REQUEST DATA PARITY ERROR MASK The mask bit for the PHY Request Data Parity
Error bit (DPE) of Interrupt Condition Register (ICR)
CONTROL BUS DATA PARITY ERROR MASK The mask bit for the Control Bus Data Parity Error bit
(CPE) of the Interrupt Condition Register (ICR)
CONTROL BUS WRITE COMMAND REJECT MASK The mask bit for the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR)
CONDITIONAL WRITE INHIBIT MASK The mask bit for the Conditional Write Inhibit bit (CWI) of the
Interrupt Condition Register (ICR)
LINK ERROR MONITOR THRESHOLD MASK The mask bit for the Link Error Monitor Threshold bit
(LEMT) of the Interrupt Condition Register (ICR)
RECEIVE CONDITION A MASK The mask bit for the Receive Condition A bit (RCA) of the Interrupt
Condition Register (ICR)
RECEIVE CONDITION B MASK The mask bit for the Receive Condition B bit (RCB) of the Interrupt
Condition Register (ICR)
USER DEFINABLE INTERRUPT MASK The mask bit for the User Definable Interrupt bit (UDI) of the
Interrupt Condition Register (ICR)
READ
Always
D5
RCAM
e
D4
LEMTM
GND) when one or more bits within the Interrupt Condition Register (ICR) are set to
WRITE
Always
D3
CWIM
26
Description
D2
CCRM
D1
CPEM
D0
DPEM