dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 73

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

6 0 Pin Descriptions
CONTROL BUS INTERFACE
The Control Bus Interface consists of I O signals used to connect the PLAYER device to Station Management (SMT)
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor It provides
access to 32 8-bit internal registers
Refer to Figure 22 Control Bus Timing Diagram for further information
Symbol
CE
R W
ACK
INT
CBA4
CBA3
CBA2
CBA1
CBA0
CBPE
CBP
CBD7
CBD6
CBD5
CBD4
CBD3
CBD2
CBD1
CBD0
Pin No
113
112
123
114
128
127
126
125
124
131
130
21
10
9
8
6
5
3
2
I O
I O
I O
O
O
I
I
I
I
(Continued)
Chip Enable An active-low TTL input signal which enables the Control Bus port for a
read or write cycle R W CBA
is low
Read E Write A TTL input signal which indicates a read Control Bus cycle (R W
or a write Control Bus cycle (R W
held valid until ACK becomes low
E Acknowledge An active low TTL open drain output signal which indicates the
completion of a read or write cycle
During a read cycle CBD
During a write cycle a microprocessor must hold CBD
low
Once ACK is low it will remain low as long as CE remains low (CE
E Interrupt An active low open drain TTL output signal indicating that an interrupt
condition has occurred The Interrupt Condition Register (ICR) should be read in order to
determine the source of the interrupt Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR)
Control Bus Address TTL input signals used to select the address of the register to be
read or written
CBA4 is the most significant bit and CBA0 is the least significant bit of the address
signals
These signals must be valid when CE is low and held valid until ACK becomes low
Control Bus Parity Enable A TTL input signal which during write cycles will enable or
disable the Control Bus parity checker Note that the Control Bus will always generate
parity during read cycles regardless of the state of this signal
Control Bus Parity A bidirectional TTL signal representing odd parity for the Control
Bus data (CBD
During a read cycle the signal is held valid by the PLAYER device as long as ACK is low
During a write cycle the signal must be valid when CE is low and must be held valid until
ACK becomes low If incorrect parity is used during a write cycle the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (ICR)
Control Bus Data Bidirectional TTL signals containing the data to be read from or
written to a register
During a read cycle the signal is held valid by the PLAYER device as long as ACK is low
During a write cycle the signal must be valid when CE is low and must be held valid until
ACK becomes low
k
7 0
l
)
73
k
7 0
k
l
4 0
are valid as long as ACK is low (ACK
e
l
0) This signal must be valid when CE is low and
Description
CBP and CBD
k
k
7 0
7 0
l
l
must be valid at the time CE
valid until ACK becomes
e
0)
e
0)
e
1)