dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 70

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

6 0 Pin Descriptions
SERIAL INTERFACE
The Serial Interface consists of I O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)
sublayer
The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX) Fiber Optic Receiver (FORX) Clock
Recovery Device (CRD device) and Clock Distribution Device (CDD device)
Symbol
CD
TTLSD
RXD
RXD
TXD
TXD
ELB
LBD
LBD
TEL
TXE
a
b
a
b
b
a
Pin No
57
58
63
64
69
70
59
66
67
77
86
I O
O
O
O
O
I
I
I
I
(Continued)
Clock Detect A TTL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXC
Signal Detect A TTL input signal from the Clock Recovery Device indicating that a
signal is being received by the Fiber Optic Receiver
Receive Data Differential 100K ECL 125 Mbps serial data input signals from the Clock
Recovery Device
Transmit Data Differential 100K ECL 125 Mbps serial data output signals to the Fiber
Optic Transmitter
External Loopback Enable A TTL output signal to the Clock Recovery Device which
enables disables loopback data through the Clock Recovery Device This signal is
controlled by the Mode Register
Loopback Data Differential 100K ECL 125 Mbps serial external loopback data output
signals to the Clock Recovery Device
When the PLAYER device is not in external loopback mode the LBD
high and the LBD
FOTX Enable Level A TTL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level
FOTX Enable A TTL output signal to enable disable the Fiber Optic Transmitter The
output level of the TXE pin is determined by three parameters the Transmit Enable (TE)
bit in the Mode Register the TM2 – TM0 bits in the Current Transmit State Register and
also the input to the TEL pin
The following rules summarizes the output of the TXE pin
(1) If TE
(2) If TE
(3) If TE
(4) If TE
(5) If TE
(6) If TE
e
e
e
e
e
e
0 and TEL
0 and TEL
1 and OTM and TEL
1 and OTM and TEL
1 and not OTM and TEL
1 and not OTM and TEL
b
signal is kept low
g
) is properly synchronized with the Receive Data (RXD
70
e
e
GND then TXE
V
CC
then TXE
e
e
GND then TXE
V
Description
e
e
CC
GND then TXE
V
then TXE
CC
e
e
GND
V
then TXE
CC
e
e
GND
V
e
e
CC
V
GND
CC
a
signal is kept
g
)