dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 42

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
STATE THRESHOLD REGISTER (STR)
The State Threshold Register contains the start value of the State Counter This counter is used in conjunction with the State
Prescale Counter to count the Line State duration The State Counter will decrement every 80 ns if the State Prescale Counter is
zero and the current Line State is Halt Line Idle Line State Master Line State Quiet Line State or No Signal Detect State The
State Counter takes
to reach zero during a continuous line state condition
The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true
(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State Idle Line State
or
(2) A line state change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or
or
(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the State Prescale Threshold register is loaded into the State Prescale Counter if the State Prescale
Counter reaches zero
The State Counter and State Prescale Counter will reset by reloading the threshold values if a Line State change occurs and the
new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect
ACCESS RULES
D0
D1 – 5
D6
D7
Master Line State Quiet Line State or No Signal Detect
No Signal Detect
D7
ST7
ADDRESS
Bit
11h
D6
ST6
(Continued)
ST0
ST1 – 5
ST6
RES
Symbol
READ
Always
D5
ST5
D4
ST4
WRITE
Always
STATE THRESHOLD BIT
for the State Counter
STATE THRESHOLD BIT
State Counter
STATE THRESHOLD BIT
for the State Counter
RESERVED Reserved for future use
Note Users are discouraged from using this bit Write data is ignored since the reserved
bit is permanently set to 0
((SPTR
a
1) x (STR
D3
ST3
42
a
1)) x 80 ns
D2
ST2
k
k
k
0
1 – 5
6
l
l
Description
l
Least significant bit (LSB) of the start value
Most significant bit (MSB) of the start value
Intermediate bits of start value for the
D1
ST1
D0
ST0