dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 48

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

D0
D1
D2
D3
D4 – 7
5 0 Registers
USER DEFINABLE REGISTER (UDR)
The User Definable Register is used to monitor and control events which are external to the PLAYER device
The value of the Sense Bits reflects the asserted deasserted state of their corresponding Sense pins On the other hand the
Enable bits assert deassert the Enable pins
ACCESS RULES
Bit
D7
RES
ADDRESS
17h
Symbol
SB0
SB1
EB0
EB1
RES
D6
RES
(Continued)
SENSE BIT 0 This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (i e SP0
160 ns Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus
Interface even if the signal is deasserted This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner
SENSE BIT 1 This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i e SP1
160 ns Once the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus
Interface even if the signal is deasserted This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner
ENABLE BIT 0 The Enable Bit 0 allows control of external logic through the Control Bus Interface The
User Definable Enable Pin 0 (EP0) is asserted deasserted by this bit
ENABLE BIT 1 This bit allows control of external logic through the Control Bus Interface The User
Definable Enable Pin 0 (EP0) is asserted deasserted by this bit
RESERVED Reserved for future use The reserved bit is set to 0 during the initialization process
(i e RST
Note Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the
PLAYER device
0 EP0 is deasserted (i e EP0
1 EP0 is asserted (i e EP0
0 EP1 is deasserted (i e EP1
1 EP1 is asserted (i e EP1
READ
Always
D5
RES
e
GND)
D4
RES
WRITE
Always
e
e
e
e
V
V
CC
CC
D3
EB1
GND)
GND)
)
)
48
Description
D2
EB0
D1
SB1
D0
SB0
e
e
V
V
CC
CC
) for a minimum of
) for a minimum of