dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 53

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)
The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface
The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i e RCCRA
during a Control Bus Interface read-cycle of RCRA
During a Control Bus Interface write-cycle the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs
from the value of the corresponding bit in the Receive Condition Comparison Register A
ACCESS RULES
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D7
LSUPIC
ADDRESS
1Ch
Symbol
NSDC
QLSC
HLSC
MLSC
NLSC
NTC
LSCC
LSUPIC
D6
LSCC
(Continued)
Always
READ
D5
NTC
NO SIGNAL DETECT COMPARISON The comparison bit for the No Signal Detect bit
(NSD) of the Receive Condition Register A (RCRA)
QUIET LINE STATE COMPARISON The comparison bit for the Quiet Line State bit
(QLS) of the Receive Condition Register A (RCRA)
HALT LINE STATE COMPARISON The comparison bit for the Halt Line State bit (HLS)
of the Receive Condition Register A (RCRA)
MASTER LINE STATE COMPARISON The comparison bit for the Master Line State bit
(MLS) of the Receive Condition Register A (RCRA)
NOISE LINE STATE COMPARISON The comparison bit for the Noise Line State bit
(NLS) of the Receive Condition Register A (RCRA)
NOISE THRESHOLD COMPARISON The comparison bit for the Noise Threshold bit
(NT) of the Receive Condition Register A (RCRA)
LINE STATE CHANGE COMPARISON The comparison bit for the Line State Change
bit (LSC) of the Receive Condition Register A (RCRA)
LINE STATE UNKNOWN
Line State Unknown
(RCRA)
D4
NLSC
WRITE
Always
D3
MLSC
PHY Invalid bit (LSUPI) of the Receive Condition Register A
53
PHY INVALID COMPARISON The comparison bit for the
D2
HLSC
Description
D1
QLSC
D0
NSDC
e
RCRA)