dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 35

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION REGISTER B (RCRB)
The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block
When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line
States are not clear by the PLAYER device thereby maintaining a record of the Line States detected
The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register B is set to 1 and the corresponding mask bits in Receive Condition Mask Register B (RCMRB) is
also set to 1
ACCESS RULES
D0
D1
D2
D3
D4
D5
D6
D7
D7
RES
ADDRESS
Bit
0Ah
D6
SILS
(Continued)
ILS
ST
ALS
LSUPV
CSE
EBOU
SILS
RES
Symbol
READ
Always
D5
EBOU
WRITE
Conditional
D4
CSE
IDLE LINE STATE Received a minimum of two consecutive Idle symbol
pairs (11111 11111)
STATE THRESHOLD This bit will be set to 1 by the PLAYER device when
the internal State Counter reaches zero It will remain set until a value equal
to or greater than one is loaded into the State Threshold Register or State
Prescale Threshold Register and this register is cleared
During the reset process (i e RST
initialized to 0 the State Threshold bit is set to 1
ACTIVE LINE STATE Received a JK symbol pair (11000 10001) and
possibly data symbols following
LINE STATE UNKNOWN
the minimum conditions to enter a know line state when the most recently
known line state was one of the following line states Active Line State or Idle
Line State
CASCADE SYNCHRONIZATION ERROR When a synchronization error
occurs the Cascade Synchronization Error bit is set to 1
A synchronization error occurs if the Cascade Start signal (CS) is not asserted
within approximately 80 ns of Cascade Ready (CR) release
ELASTICITY BUFFER UNDERFLOW OVERFLOW The Elasticity Buffer
has either overflowed or underflowed The Elasticity Buffer will automatically
recover if the condition which caused the error is only transient
SUPER IDLE LINE STATE Received a minimum of eight Idle symbol pairs
(11111 11111)
RESERVED Reserved for future use The reserved bit is set to 0 during the
reset process
Note Users are discouraged from using this bit It may be set or cleared without any
effects to the functionality of the PLAYER device
D3
LSUPV
35
D2
ALS
PHY VALID Receiver Block has not detected
Description
e
GND) since the State Counter is
D1
ST
D0
ILS