dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 51

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
INTERRUPT CONDITION COMPARISON REGISTER (ICCR)
The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface
The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison
Register (i e ICCR
During a Control Bus Interface write-cycle the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the
value of the corresponding bit in the Interrupt Condition Comparison Register
ACCESS RULES
D0
D1
D2
D3
D4
D5
D6
D7
D7
UDIC
ADDRESS
1Ah
Bit
D6
RCBC
e
ICR) during a Control Bus Interface read-cycle of ICR
(Continued)
DPEC
CPEC
CCRC
CWIC
LEMTC
RCAC
RCBC
UDIC
Symbol
READ
Always
D5
RCAC
D4
LEMTC
WRITE
Always
PHY REQUEST DATA PARITY ERROR COMPARISON The comparison
bit for the PHY Request Data Parity Error bit (DPE) of the Interrupt Condition
Register (ICR)
CONTROL BUS DATA PARITY ERROR COMPARISON The comparison bit
for the Control Bus Data Parity Error bit (CPE) of the Interrupt Condition
Register (ICR)
CONTROL BUS WRITE COMMAND REJECT COMPARISON The
comparison bit for the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR)
CONDITIONAL WRITE INHIBIT COMPARISON The comparison bit for the
Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR)
LINK ERROR MONITOR THRESHOLD COMPARISON The comparison bit
for the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition
Register (ICR)
RECEIVE CONDITION A COMPARISON The comparison bit for the
Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR)
RECEIVE CONDITION B COMPARISON The comparison bit for the
Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR)
USER DEFINABLE INTERRUPT COMPARISON The comparison bit for the
User Definable Interrupt bit (UDIC) of the Interrupt Condition Register (ICR)
D3
CWIC
51
D2
CCRC
Description
D1
CPEC
D0
DPEC