dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 62

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

6 0 Pin Descriptions
CLOCK INTERFACE
The Clock Interface consists of 12 5 MHz and 125 MHz clocks used by the PLAYER device The clocks are generated by either
the Clock Distribution Device or Clock Recovery Device
Symbol
LBC
RXC
RXC
TXC
TXC
TBC
TBC
a
b
a
b
a
b
Pin No
57
36
37
48
49
51
52
I O
I
I
I
I
(Continued)
Local Byte Clock A TTL 12 5 MHz 50% duty cycle input clock from the Clock
Distribution Device The Local Byte Clock is used by the PLAYER device’s internal
CMOS logic and to latch incoming outgoing data of the Control Bus Interface Port A
Interface Port B Interface and other miscellaneous I Os
Receive Bit Clock Differential 100k ECL 125 MHz clock input signals from the Clock
Recovery Device The Receive Bit Clock is used by the Serial Interface to latch the
Receive Data (RXD
Transmit Bit Clock Differential 100k ECL 125 MHz clock input signals from the Clock
Distribution Device The Transmit Bit Clock is used by the Serial Interface to latch the
Transmit Data (TXD
Transmit Byte Clock Differental 100k ECL 12 5 MHz clock input signals from the Clock
Distribution Device The Transmit Byte Clock is used by the PLAYER device’s internal
Shift Register Block
g
g
)
)
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Description