dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 36

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION MASK REGISTER A (RCMRA)
The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1
Since this register is cleared (i e set to 0) during the reset process all interrupts are initially masked
ACCESS RULES
D0
D1
D2
D3
D4
D5
D6
D7
D7
LSUPIM
ADDRESS
Bit
0Bh
D6
LSCM
(Continued)
NSDM
QLSM
HLSM
MLSM
NLSM
NTM
LSCM
LSUPIM
Symbol
READ
Always
D5
NTM
D4
NLSM
WRITE
Always
NO SIGNAL DETECT MASK The mask bit for the No Signal Detect bit (NSD)
of the Receive Condition Register A (RCRA)
QUIET LINE STATE MASK The mask bit for the Quiet Line State bit (QLS) of
the Receive Condition Register A (RCRA)
HALT LINE STATE MASK The mask bit for the Halt Line State bit (HLS) of
the Receive Condition Register A (RCRA)
MASTER LINE STATE MASK The mask bit for the Master Line State bit
(MLS) of the Receive Condition Register A (RCRA)
NOISE LINE STATE MASK The mask bit for the Noise Line State bit (NLS)
of the Receive Condition Register A (RCRA)
NOISE THRESHOLD MASK The mask bit for the Noise Threshold bit (NT) of
the Receive Condition Register A (RCRA)
LINE STATE CHANGE MASK The mask bit for the Line State Change bit
(LSC) of the Receive Condition Register A (RCRA)
LINE STATE UNKNOWN
State Unknown
(RCRA)
D3
MLSM
36
PHY Invalid bit (LSUPI) of the Receive Condition Register A
D2
HLSM
PHY INVALID MASK The mask bit for the line
Description
D1
QLSM
D0
NSDM