tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 145

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4 Operation
10.4.1
This section describes the operation of the DMAC.
Overview
between I/O peripherals and memory without intervention of the TX19 core processor.
(1) Devices Supported for the Source and Destination
(2) Exchanging Bus Mastership (Bus Arbitration)
The DMAC is a high-speed 32-bit DMA controller used to quickly move large blocks of data
peripherals. The device from which data is transferred is referred to as a source device, and the
device to which data is transferred is referred to as a destination device. Both memory and I/O
peripherals can be a source or destination device. The DMAC supports data transfers from memory
to I/O peripherals, from I/O peripherals to memory, and from memory to memory, but not from I/O
peripherals to I/O peripherals.
the DMAC asserts the DACKn (n = channel number) signal to indicate that data is being
transferred in response to a previous transfer request. Because each DMA channel has only one
requesting an interrupt to the TX19 core processor. If so programmed, the Interrupt Controller
(INTC) forwards a DMA request to the DMAC (see 10.4.6, Interrupts). The DMA request coming
from the INTC is cleared when the INTC receives a DACKn from the DMAC. Consequently, a
DMA request for a transfer to/from an I/O peripheral is cleared after each DMA bus cycle (i.e.,
every time the number of bytes programmed into the CCRn.TrSiz field is transferred). On the other
hand, during memory-to-memory transfer, the DACKn signal is not asserted until the byte count
register (BCRn) reaches zero. Therefore, memory-to-memory transfer can continuously move large
blocks of data in response to a single DMA request.
memory is discontinued after every DMA bus cycle. Nonetheless, until the BCRn register reaches
zero, the DMAC remains in Ready state to wait for the next transfer request.
When the DMAC receives a bus grant signal from the TX19 core processor, it assumes bus
mastership to service the DMA request. There are two bus request signals from the DMAC going
to the TX19 core processor. One is a bus request without snooping (GREQ), and the other is a bus
request with snooping (SREQ). The SReq bit in the CCRn register is used to select a bus request
signal to use for each DMA channel.
request to the DMAC. The RelEn bit of the CCRn register controls whether to honor this request
on a channel-by-channel basis. This setting has a meaning only when a DMA channel uses GREQ
(i.e., a bus request without snooping). It has no meaning or effect when a DMA channel uses
SREQ (i.e., a bus request with snooping) because, in this case, the TX19 core processor does not
have the capability to generate a bus release request.
request to be serviced.
DACKn signal, the DMAC can not handle data transfers between two I/O peripherals.
Note 1: The NMI interrupt is left pending while the DMAC has control of the bus.
Note 2: Don’t place the TMP1940CYAF in Halt powerdown mode while the DMAC is operating.
The DMAC handles data transfers from memory to memory and between memory and I/O
DMA protocols for memory and I/O peripherals differ in that when accessing an I/O peripheral,
Interrupt requests can be programmed to be a trigger to initiate a DMA process instead of
For example, data transfers between the TMP1940CYAF on-chip peripheral and on- or off-chip
In response to a DMA request, the DMAC issues a bus request to the TX19 core processor.
While the DMAC has control of the bus, the TX19 core processor may issue a bus release
The DMAC relinquishes the bus to the TX19 core processor when there is no pending DMA
TMP1940CYAF-103
TMP1940CYAF