tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 189

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TB0MOD
(0xFFFF_F182)
Name
Read/Write
Reset Value
Function
Must be written as 00.
7
0
R/W
Figure 12.7 TMRB0 Mode Register
6
0
TMRB0 Mode Register
TMP1940CYAF-147
Software
capture
0: Capture
1: Don’t
TB0CP0
care
Up-counter (UC0) clear control
Capture triggers
Software capture
W*
5
1
00
01
10
11
0
1
0
1
Capture triggers
00: Disabled
01: TB0IN0 TB0IN1
10: TB0IN0 TB0IN0
11: TA1OUT TA1OUT
Disabled
UC0 is reset upon a match with TB0RG1.
Capture disabled
Latches UC0 value into TB0CP0 at rising edges of TB0IN0
Latches UC0 value into TB0CP1 at rising edges of TB0IN1.
Latches UC0 value into TB0CP0 at rising edges of TB0IN0.
Latches UC0 value into TB0CP1 at falling edges of TB0IN0.
Latches UC0 value into TB0CP0 at rising edges of TA1OUT.
Latches UC0 value into TB0CP1 at falling edges of TA1OUT.
Latches UC0 value into TB0CP0.
Don’t care
TB0CPM1 TB0CPM0
4
0
3
0
UC0 clear
control
0: Disable
1: Enable
TB0CLE
TMP1940CYAF
R/W
2
0
TMRB0 clock source
00: TB0IN0 input
01: T1
10: T4
11: T16
TB0CLK1
1
0
TB0CLK0
0
0