tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 297

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

18.6 SIO Timing
SCK Output Mode /
Active-High SCL
Active-Low SCK
18.6.1
Input Mode
Input Mode
Transmit Data
SCLK
SCLK
Receive Data
I/O Interface Mode
programming of the clock gear function.
(1) SCLK Input Mode
(2) SCLK Output Mode
(RxD)
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
(TxD)
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall* t
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall* t
SCLK period (programmable)
TxD data to SCLK rise
TxD data hold after SCLK rise
RxD data valid to SCK rise
RxD data hold after SCK rise
In the tables below, the letter x represents the fsys cycle period, which varies, depending on the
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP1940CYAF-255
t
t
t
t
t
t
t
t
Symbol
Symbol
SCY
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
(t
VALID
SCY
1
(tSCY/2)
(tSCY/2)
(t
1
SCY
/2)
2x
x
Min
Min
Equation
16x
Equation
16x
/2)
t
0
0
HSR
23
5x
8
t
OHS
3x
15
15
23
Max Min Max Min Max
Max Min Max Min Max
VALID
2
2
800
127
550
108
800
385
385
73
20 MHz
20 MHz
0
0
TMP1940CYAF
500
343
500
235
235
71
71
54
32 MHz
32 MHz
0
0
VALID
3
3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns