tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 247

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.5 I
14.5.1
14.5.2
14.5.3
2
C Bus Mode Configuration
Acknowledgment Mode
generates a clock pulse for acknowledge automatically after each data. As a transmitter, the SBI
releases the SDA line during this acknowledge cycle so that the receiver of the data transfer can drive
the SDA line low to acknowledge receipt of the data. As a receiver, the SBI pulls the SDA line low
during the acknowledge cycle after each data has been received.
SBI does not generate acknowledge clock pulses.
Number of Bits Per Transfer
received. After a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction
(
a previously programmed value.
Serial Clock
(1) I
R
Setting the SBI0CR1.ACK bit selects Acknowledge mode. When operating as a master, the SBI
Clearing the SBI0CR1.ACK bit selects Non-Acknowledge mode. When operating as a master, the
The SBI0CR1.BC[2:0] field specifies the number of bits of the next data item to be transmitted or
/
W
the SCL pin in master mode, as illustrated below.
2
C Bus Clock Source
) bit to be transferred in a packet of eight bits. At other times, the SBI0CR1.BC[2:0] field keeps
The SBI0CR1.SCK[2:0] field controls the maximum frequency of the SCL clock driven out on
t
t
fscl = 1/(t
LOW
HIGH
=
= 2
= 2
2
Figure 14.7 I
n – 1
n
Low
T
n – 1
t
HIGH
0
4
/ T0
/ T0
t
TMP1940CYAF-205
HIGH
4/ T0
)
t
2
LOW
C Bus Clock Source
SBI0CR1.SCK[2:0]
000
001
010
011
100
101
110
1/fscl
TMP1940CYAF
10
n
4
5
6
7
8
9