tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 86
tmp1940cyaf
Manufacturer Part Number
tmp1940cyaf
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP1940CYAF.pdf
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7.3
Port 2 (P20–P27)
A[0:7] bits of the address bus or the A[16:23] bits of the address bus. The P2CR and P2FC registers select
the direction and function of the Port 2 pins. Upon reset, the Output Latch (P2) is set to all 1s, and the P2CR
and P2FC register bits are cleared, configuring all Port 2 pins as input port pins.
Eight Port 2 pins can be individually programmed to function as discrete general-purpose I/O pins, the
For external memory accesses, Port 2 pins must be configured as A[0:7] or A[16:23].
Direction Control
Function Control
P2FC Write
P2CR Write
Output Latch
P2 Write
(bitwise)
(bitwise)
Reset
A16–23
A0–7
Figure 7.5 Port 2 (P20~P27)
B
A
TMP1940CYAF-44
S
Y
P2 Read
A
B
S
Y
Output Buffer
TMP1940CYAF
Port 2
P20–P27
(A0–A7/A16–A23)
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