tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 434

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.7.10
3.7.11
Auto Program Command
basis. In the fourth bus cycle of the Auto Program command sequence, the program address is latched
on the falling edge of
data initiates the embedded Auto Program algorithm. The Auto Program command executes a sequence
of internally timed events to program the desired bits of the addressed memory location and verify that
the desired bits are sufficiently programmed. The system can determine the status of the programming
operation by using write status flags (see Table 3.28 on page 82).
terminates the programming operation. The programming operation that was interrupted should be re-
initiated once the flash memory is ready to accept another command sequence because data may be
corrupted.
program a protected block, the Auto Program command does nothing; the flash memory returns to Read
mode in approximately 3 m after the rising edge of
sequence.
back to a 1. Only an erase operation can change a 0 back to a 1. A programming failure condition is
indicated if the system tries to program a 1 to a location that was previously programmed to a 0. Note
that this is not a device failure condition since the flash memory was used incorrectly.
Embedded Operation mode. The system can determine this status by using write status flags. To put the
flash memory back in Read mode, use the Read/Reset command to reset the flash memory or a hardware
reset to reset the whole chip. In case of a programming failure, it is recommended to replace the chip or
discontinue the use of the failing flash block.
Auto Chip Erase Command
of the command sequence. The embedded Auto Chip Erase algorithm automatically preprograms the
entire memory for an all-0 data pattern prior to the erase; then, it automatically erases and verifies the
entire memory for an all-1 data pattern. The system can determine the status of the chip erase operation
by using write status flags (see Table 3.28 on page 82).
terminates the chip erase operation. The chip erase operation that was interrupted should be re-initiated
once the flash memory is ready to accept another command sequence because data may be corrupted.
erases the unprotected blocks and ignores the protected blocks. If all the blocks are protected, the Auto
Chip Erase command does nothing; the flash memory returns to Read mode in approximately 100 m
after the rising edge of
Any commands written during the chip erase operation are ignored. A hardware reset immediately
The block protection feature disables erase operations in any block. The Auto Chip Erase algorithm
In Programmer mode, the programming of the flash array is performed on a halfword-by-halfword
Any commands written during the programming operation are ignored. A hardware reset immediately
The block protection feature disables programming operations in any block. If an attempt is made to
A bit must be programmed to change its state from a 1 to a 0. A bit can not be programmed from a 0
When the embedded Auto Program algorithm is complete, the flash memory returns to Read mode.
If any failure occurs during the programming operation, the flash memory remains locked in
The embedded Auto Chip Erase algorithm is initiated on the rising edge of
When the embedded Auto Chip Erase algorithm is complete, the flash memory returns to Read mode.
After a reset, the flash memory is set to Read mode if
Standby mode if
held at the high-impedance state. Any command sequence must be written after the flash
memory is put back in Read mode.
WE
WE
RESET
, and data is latched on the rising edge of
in the sixth bus cycle of the command sequence.
TMP1940FDBF-76
is at the V
IL
level. While
WE
RESET
in the fourth bus cycle of the command
RESET
is at the V
WE
TMP1940FDBF
. The latching of the program
is at the V
WE
IL
in the sixth bus cycle
level, D0 to D15 are
IH
level and to