zl50415 Zarlink Semiconductor, zl50415 Datasheet

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... Frame Engine /100 RMII Ports Figure 1 - ZL50418 System Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Managed 16-Port 10/100 M + 2-Port 1 G ZL50418/GKC 553-pin HSBGA • Provides port based and ID tagged VLAN support (IEEE 802.1Q 255 VLANs • ...

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... Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-in self test for internal and external SRAM 2 • EEPROM for configuration • 553 BGA package ZL50418 2 Zarlink Semiconductor Inc. Data Sheet ...

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... SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50418 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50418 is packaged in a 553-pin Ball Grid Array package. ZL50418 3 Zarlink Semiconductor Inc. Data Sheet ...

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... Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.4 VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 MAC Address Filtering 5.5 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 Priority Classification Rule 5.7 Port and Tag Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8 Port-Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8.1 Tag-Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.9 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ZL50418 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 LED Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.2 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2 EEE 802.3 HUB Management (RFC 1516 13.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.3 FCSErrors 13.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ZL50418 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.4.2 AVTCH – VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.4.3 PVMAP00_0 – Port 00 Configuration Register 14.4.4 PVMAP00_1 – Port 00 Configuration Register 14.4.5 PVMAP00_3 – Port 00 Configuration Register 14.5 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.5.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.5.2 PVROUTE ZL50418 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...

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... INTP_MASK1 – Interrupt Mask for MAC Port 2 14.7.10 INTP_MASK2 – Interrupt Mask for MAC Port 4 14.7.11 INTP_MASK3 – Interrupt Mask for MAC Port 6 14.7.12 INTP_MASK4 – Interrupt Mask for MAC Port 8 14.7.13 INTP_MASK5 – Interrupt Mask for MAC Port 10, ZL50418 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... RDRC0 – WRED Rate Control 14.9.39 RDRC1 – WRED Rate Control 14.9.40 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.9.40.1 USER_PORT0_(0~7) – User Define Logical Port (0~7 14.9.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . . 97 ZL50418 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...

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... TBI Registers 111 14.13.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.13.2 Status Register 112 14.13.3 Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.13.4 Link Partner Ability Register 113 14.13.5 Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.13.6 Extended Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 15.1 BGA Views (TOP Views 115 ZL50418 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...

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... Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15.8.2 Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 15.8.3 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.8.4 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.8.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2 15.8 Input Setup Timing 160 15.8.7 Serial Interface Setup Timing 161 ZL50418 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 38 - MDIO Input Setup and Hold Timing 159 Figure 39 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2 Figure Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2 Figure Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 42 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 43 - Serial Interface Output Delay Timing 161 ZL50418 List of Figures 11 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 26 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 27 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 29 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2 Table Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 30 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 32 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ZL50418 List of Tables 12 Zarlink Semiconductor Inc. Data Sheet ...

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... Transmit processes. The PCS Auto negotiation process allows the ZL50418 to exchange configuration information between two devices that share a link segment and to automatically configure the link for the appropriate speed of operation for both devices. ZL50418 13 Zarlink Semiconductor Inc. Data Sheet ...

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... MAC address Control Table (MCT) Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. Note that the external MAC table is located in the external SSRAM Memory. ZL50418 14 Zarlink Semiconductor Inc. Data Sheet 2 C interface, which ...

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... INTERNAL CPU CONFIGUE FRAME REGISTERS RECEIVE TRANSMIT FIFO Figure 2 - Overview of the CPU Interface 15 Zarlink Semiconductor Inc. Data Sheet CONTROL BLOCK REG 8/16 bit internal data bus 8/16 bit internal data bus CONTROL CPU CONTROL COMMAND FRAME COMMAND ...

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... Note: Memory read and write requests by the CPU may include VLAN table, spanning tree, statistic counters and similar updates. In addition, there are nine types of Control frames generated by the ZL50418 and sent to the CPU: • Interrupt CPU when statistics counter rolls over • Response to memory read request from CPU ZL50418 16 Zarlink Semiconductor Inc. Data Sheet ...

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... If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. ZL50418 RW ACK DATA1 (8bits) ACK DATA 2 17 Zarlink Semiconductor Inc. Data Sheet 2 C interface at ACK DATA M ACK STOP 2 C Interface ...

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... Any command can be aborted in the middle by sending an ABORT pulse to the ZL50418. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall. An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall. ZL50418 18 Zarlink Semiconductor Inc. Data Sheet ...

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... FDB reservations and usage, as well as TxQ occupancy ZL50418 A11 W A9 A10 COMMAND DATA Figure 4 - Write Command R A10 A11 A9 COMMAND DATA Figure 5 - Read Command 19 Zarlink Semiconductor Inc. Data Sheet 2 Extra clocks after last transfer ...

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... When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. ...

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... When the CPU writes an entry to the VLAN Index Mapping Table it has to write the same data in bank A and bank B. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be performed by either bank at any time without a problem. ZL50418 SRAM Bank B TXDMA RXDMA 8-15 0-7 21 Zarlink Semiconductor Inc. Data Sheet RXDMA 8-15 ...

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... M 0 Bank Bank B 1.5 M 1 Tag based VLAN Enable Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area VLAN Table Area Figure 7 - Memory Map 22 Zarlink Semiconductor Inc. Data Sheet Max MAC Address 63.5 K ...

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... But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. As stated earlier, when all the information is compiled, the switch response is generated. The search engine also interacts with the CPU with regard to learning and aging. ZL50418 23 Zarlink Semiconductor Inc. Data Sheet ...

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... The table below provides a mapping from VLAN ID to VLAN index maintained by system software and is checked by the hardware search engine for every incoming frame. This table has 4 K entries and is stored in external SRAM organized as 512  8 entries (total VLAN indexes) as shown. Each VLAN index is 8 bits. ZL50418 24 Zarlink Semiconductor Inc. Data Sheet ...

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... ZL50418 VIX4 VIX3 … … … … … … VIX4092 VIX4091 G0 CPU P15 P14 Zarlink Semiconductor Inc. Data Sheet VIX2 VIX1 VIX0 … … … … … … VIX4090 VIX4089 VIX4088 …… ...

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... In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications such as VoIP. ZL50418 26 Zarlink Semiconductor Inc. Data Sheet ...

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... Yes Use Logical Port Use VLAN Priority Use Logical Port Figure 8 - Priority Classification Rule Destination Port Numbers Bit Map 26 … Table 4 - Port-Based VLAN 27 Zarlink Semiconductor Inc. Data Sheet Use Default Port Settings IP Frame ? Yes No Use TOS Yes ...

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... Table 5 - Supported Memory Configurations (Pipeline SBRAM Mode) ZL50418 2 M per bank (Bootstrap pin TSTOUT7 = pull down) Two 256 SRAM/bank Four 128 SRAM/bank or Two 128 SRAM/bank 28 Zarlink Semiconductor Inc. Data Sheet Connections Connect 0E# and WE# Connect 0E0# and WE0# Connect 0E1# and WE1# ...

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... M (SRAM) ZL50415 X ZL50416 X ZL50417 ZL50418 Table 6 - Options for Memory Configuration BANK A (1M One Layer) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, TSTOUT4 = Open Figure 9 - Memory Configuration For: 2 Banks, 1 Layer Total ...

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... Address LB_A[19:3] BANK B (2M One Layer) Data LB_D[63:32] Data LB_D[31:0] SRAM Memory Memory 256 K 256 K 32 bits 32 bits Address LB_A[20:3] 30 Zarlink Semiconductor Inc. Data Sheet SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits Memory 256 K 32 bits ...

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... Upon receiving an end of frame that is good, the Rx interface makes a switch request. 6.2.3 RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. ZL50418 31 Zarlink Semiconductor Inc. Data Sheet ...

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... Low Drop Probability (low-drop) defined) Apps: phone calls, circuit emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. 32 Zarlink Semiconductor Inc. Data Sheet The TxQ manager can also High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to ...

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... Drop: No drop if P2 not oversubscribed. Apps: emails, file backups. Latency: < desired, but not critical. Drop: No drop if P1 not oversubscribed. 33 Zarlink Semiconductor Inc. Data Sheet High Drop Probability (high-drop) Apps: non-critical interactive apps. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise ...

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... To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) ZL50418 P2 P1 Delay Bound WFQ Delay Bound WFQ 34 Zarlink Semiconductor Inc. Data Sheet ...

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... With reference to Table 7, only the middle two QoS configurations may be used. Peak rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the peak rate for shaped traffic is 32/64 * 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number, ZL50418 35 Zarlink Semiconductor Inc. Data Sheet ...

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... Suppose we wish this limit kilobytes. The number of bytes is measured in 8-byte increments, so the 16-bit field “Maximum burst size” is set to (12000/8) 1500. ZL50418 31:16 Maximum burst size 36 Zarlink Semiconductor Inc. Data Sheet 15:0 Number of bytes ...

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... When the priority section is full or the packet has priority the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port. ZL50418 BKB P1 CKB Figure 12 - Behaviour of the WRED Logic 37 Zarlink Semiconductor Inc. Data Sheet High Drop Low Drop 100% ...

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... Because frame loss is unacceptable for some applications, the ZL50418 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch to temporarily hold off. ZL50418 38 Zarlink Semiconductor Inc. Data Sheet shared pool S ...

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... Xon is triggered, and the 26-bit vector is reset to zero. The ZL50418 also provides the option of disabling VLAN multicast flow control. Note: If per-Port flow control is on, QoS performance will be affected. ZL50418 39 Zarlink Semiconductor Inc. Data Sheet ...

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... Two BE classes for 1 Gbps ports Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified Zarlink Semiconductor Inc. Data Sheet P1 P0 BE0 BE1 P0 ...

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... In unmanaged mode, 3 trunk groups are supported. Groups 0 and 1 can trunk 10/100 ports. Group 2 can trunk 2 Gigabit ports. The supported combinations are shown in the following table. Group 0 Table 13 - Select via trunk0_mode register ZL50418 Port 0 Port 1 Port Zarlink Semiconductor Inc. Data Sheet Port 3 ...

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... MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0. Refer to Port Mirroring Application Notes for further information. ZL50418       Port 4 Port 5 Port Port 25(Giga 0) Port 26 (Giga Table 15 - Unmanaged Mode 42 Zarlink Semiconductor Inc. Data Sheet  Port 7  ...

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... Figure 14. There are two TBI interfaces in the ZL50418 devices. To enable to TBI function, the corresponding TXEN and TXER pins need to be boot strapped. See Ball – Signal Description for details. M25/26_TXD[9:0] M25/26_TXCLK ZL5041x M25/26_RXD[9:0] M25/26_RXCLK M25/26_COL ZL50418 T[9:0] REFCLK R[9:0] RBC0 RBC1 Figure 14 - TBI Connection 43 Zarlink Semiconductor Inc. Data Sheet SERDES ...

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... TXD[0] TXEN 5041X Figure 15 - GPSI (7WS) Mode Connection Diagram ZL50418 crs rxd Port 0 rx_clk Ethernet tx_clk PHY txd txen Port 15 Ethernet PHY Link Serializer (CPLD) Collision Serializer (CPLD) 44 Zarlink Semiconductor Inc. Data Sheet link0 col0 link1 col1 link2 col2 link15 col15 ...

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... Bit 5: Speed (1= 100 Mb/ Mb/s) • Bit 6: Full-duplex • Bit 7: Collision Eight clocks are required to cycle through the eight status bits for each port. ZL50418 25 cycles for link/ 24 cycles for col Drived by CPLD Total 32 cycles period 45 Zarlink Semiconductor Inc. Data Sheet ...

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... LED Interface Timing Diagram The signal from the ZL50418 to the LED decoder is shown in Figure 17. Figure 17 - Timing Diagram of LED Interface ZL50418 46 Zarlink Semiconductor Inc. Data Sheet . ...

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... Frames with Length Between 128-255 Bytes B[17] A-u Frames with Length Between 256-511 Bytes B[18] B-l Frames with Length Between 512-1023 Bytes B[19] B-u Frames with Length Between 1024-1528 Bytes B[20] C-l Fragments B[21] C-U1 Alignment Error B[22] C-U Undersize Frames B[23] D-l CRC B[24] D-u Short Event B[25] E-l Collision B[26] E-u Drop B[27] F-l Filtering Counter B[28] F-U1 Delay Exceed Discard Counter ZL50418 47 Zarlink Semiconductor Inc. Data Sheet 0 ...

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... No collisions 13.2.1.2 ReadableFrame Counts number of good valid frames received. Frame size: No FCS error No collisions ZL50418 > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged 48 Zarlink Semiconductor Inc. Data Sheet ...

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... VLAN Tagged; 1518 bytes if not VLAN Tagged > 64 bytes, > 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged don’t care don’t care < 10 bytes don’t care don’t care 49 Zarlink Semiconductor Inc. Data Sheet ...

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... For repeaters or HUB application only. 13.2.1.13 TotalErrors Sum of the following errors: FCS errors Alignment errors Frame too long Short events Late events Very long events ZL50418 > 10 bytes, < 64 bytes don’t care don’t care any size any size > Jabber 50 Zarlink Semiconductor Inc. Data Sheet ...

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... BroadcastPkts Counts the number of good frames received and forwarded with broadcast address. Does not include non-broadcast multicast frames. 13.4.1.4 MulticastPkts Counts the number of good frames received and forwarded with multicast address. Does not include broadcast frames. ZL50418 51 Zarlink Semiconductor Inc. Data Sheet ...

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... VLAN tag (1518 if no VLAN) 1522 bytes if VLAN tag (1518 bytes if no VLAN) don’t care don’t care < 64 bytes don’t care > 1522 bytes if VLAN tag (1518 bytes if no VLAN) don’t care 52 Zarlink Semiconductor Inc. Data Sheet ...

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... We also have two counters, one for unicast frames sent and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “frame send fail.” This keeps track of FIFO under-runs, late collisions, and collisions that have occurred 16 times. ZL50418 any size 53 Zarlink Semiconductor Inc. Data Sheet ...

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... R/W 105 + 4N R/W 170 R/W 171-178 R/W 200 R/W 201 R/W 203 R/W 204 R/W 205 R/W 206 R/W 207 R/W 208 R/W 209 R/W 20B R/W 54 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) 000-01 020 A 01B-03 000 5 NA 000 036 000 037 081 038-052 0FF 053-06 0FF D 089-0A 007 3 0A4 ...

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... R/W 20E R/W 20F R/W 210 R/W 211 R/W 212 R/W 220 R/W 221 R/W 222 R/W 223 R/W 224 R/W 225 R/W 226 R/W 227 R/W 228 R/W 229 R/W 22A R/W 22B R/W 55 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) NA 004 NA 005 NA 006 NA 007 NA 003 NA 019 NA 01A NA 0FF NA 0FF NA 0FF NA 0FF NA 0FF NA 0FF NA 0FF ...

Page 56

... R/W 304 R/W 305 R/W 306 R/W 310+N (310 R/W -313) 323 R/W 324 RO 325 R/W 400 R/W 401 R/W 402 R/W 403 R/W 404 R/W 500 R/W 501 R/W 502 R/W 56 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) NA 0FF NA 0FF NA 0FF NA 0FF NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 ...

Page 57

... R/W 512 R/W 513 R/W 514 R/W 515 R/W 516 R/W 517- 51C R/W 51D- 522 R/W 523- 52E R/W 52F- 552 R/W 553 R/W 554 R/W 57 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) 0AD 000 0AE 000 0AF 000 0B0 000 0B1 000 0B2 000 0B3 000 0B4 000 ...

Page 58

... R/W 596 R/W 597 R/W 598 R/W 599 R/W 59A R/W 59B R/W 59C R/W 59D R/W 59E R/W 5A0-5A2 R/W 600 R/W 601 R/W 602 R/W 58 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) 0D6-0D 000 D 0DE-0E 000 5 0E6 000 0E7 000 0E8 000 0E9 000 0EA 000 0EB 000 0EC 000 ...

Page 59

... R/W 605 R/W 606 R/W 607 RO 608 RO 609 R/W 60B R/W 700 R/W 701 R/W 702 R/W 703 R/W F00 R/W F01 RO F02 RO F03 R/W F04 RO FFF RO 59 Zarlink Semiconductor Inc. Data Sheet Addr Default Notes (Hex) N/A 000 N/A 000 N/A 000 N/A 000 N/A N/A N/A N/A 0F3 000 0FF 000 N/A 07F N/A 017 N/A 0FF N/A 000 N/A 000 ...

Page 60

... Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and flushed the rest of frame fragment, If occurs. This bit will be self-cleared. Bit [4]: • Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. ZL50418 60 Zarlink Semiconductor Inc. Data Sheet ...

Page 61

... Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read Bit [3]: • Gigabit port A interrupt Bit [4]: • Gigabit port B interrupt Bit [7:3]: • Reserve Note: This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it. ZL50418 61 Zarlink Semiconductor Inc. Data Sheet ...

Page 62

... MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented. Bit [ Half Duplex - Only in 10/100 mode - 0 - Full Duplex Bit [ 10Mbps - 0 - 100Mbps ZL50418 2 C (R/ Port Mode 62 Zarlink Semiconductor Inc. Data Sheet 1 0 ...

Page 63

... WFQ credit set 2 • 11: select class byte limit set 3 and classes WFQ credit set 3 ZL50418 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned QoS Sel Reserve DisL 63 Zarlink Semiconductor Inc. Data Sheet 1 0 Ftf Futf ...

Page 64

... Gigabit port data path Direct flow control disabled (default Direct flow control enabled Bit [4]: • Reset GIGA port Normal operation (default Reset Gigabit port B ZL50418 RstA DF MiiA 64 Zarlink Semiconductor Inc. Data Sheet 0 RstA ...

Page 65

... This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default VLAN tag. If the received packet is untagged, then the packet is classified with the default VLAN tag. If the received packet has a VLAN then PVID is used to replace the packet’s VLAN ID. ZL50418 2 C (R/ (R/ (R/W) 65 Zarlink Semiconductor Inc. Data Sheet ...

Page 66

... Transmit Priority Level 2 - 011 Transmit Priority Level 3 - 100 Transmit Priority Level 4 - 101 Transmit Priority Level 5 - 110 Transmit Priority Level 6 - 111 Transmit Priority Level 7 (Highest) ZL50418 2 C (R/ Ultrust PVID 2 C (R/ Default tx priority VLAN Mask 66 Zarlink Semiconductor Inc. Data Sheet 0 0 ...

Page 67

... Discard Priority Level 0 (Lowest Discard Priority Level 1 (Highest Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS or Logical Port Transmit Priority and Discard Priority are based on values programmed in bit [6:3] 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... Bit [2]: • Disable dropping of frames with destination MAC addresses 0180C2000001 to 0180C200000F (Default = Drop all frames in this range - 1: Disable dropping of frames in this range ZL50418 STP SM0 rPCS Zarlink Semiconductor Inc. Data Sheet 0 Vmod ...

Page 69

... VLAN Index 8’hC5 has router group and the router group is VLAN Index 8’h45 Bit [6]: • VLAN Index 8’hC6 has router group and the router group is VLAN Index 8’h46 Bit [7]: • VLAN Index 8’hC7 has router group and the router group is VLAN Index 8’h47 ZL50418 69 Zarlink Semiconductor Inc. Data Sheet ...

Page 70

... VLAN Index 8’hDB has router group and the router group is VLAN Index 8’h5B Bit [4]: • VLAN Index 8’hDC has router group and the router group is VLAN Index 8’h5C Bit [5]: • VLAN Index 8’hDD has router group and the router group is VLAN Index 8’h5D ZL50418 70 Zarlink Semiconductor Inc. Data Sheet ...

Page 71

... VLAN Index 8’hF0 has router group and the router group is VLAN Index 8’h70 Bit [1]: • VLAN Index 8’hF1 has router group and the router group is VLAN Index 8’h71 Bit [2]: • VLAN Index 8’hF2 has router group and the router group is VLAN Index 8’h72 ZL50418 71 Zarlink Semiconductor Inc. Data Sheet ...

Page 72

... TRUNK0_L – Trunk group 0 Low (Managed mode only) CPU Address:h200 Accessed by CPU, serial interface (R/W) Bit [7:0] Port7-0 bit map of trunk 0. (Default 00) 14.6.2 TRUNK0_M – Trunk group 0 Medium (Managed mode only) CPU Address:h201 Accessed by CPU, serial interface (R/W) Bit [7:0] Port15-8 bit map of trunk 0. (Default 00) ZL50418 72 Zarlink Semiconductor Inc. Data Sheet ...

Page 73

... Accessed by CPU, serial interface (R/W) Bit [4:0] Hash result 0 destination port number (Default 00) ZL50418 TRUNK0_M TRUNK0_L (R/ Port Select 73 Zarlink Semiconductor Inc. Data Sheet ...

Page 74

... Accessed by CPU, serial interface and Port Select Bit [1:0]: • Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1 in unmanaged mode Reserved - 01 Port 4 and 5 are used for trunk1 - 10 Reserved - 11 Port 4,5,6 and 7 are used for trunk1 ZL50418 2 C (R/ Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... Trunk Mode. Enable Trunk group for Gigabit port 1 and 2 in managed mode. In unmanaged mode Trunk 2 is enable/disable using input pin TRUNK2. - 010 Single Ring with G1 - 100 Single Ring with G2 - 111 Dual Ring Mode ZL50418 Zarlink Semiconductor Inc. Data Sheet ...

Page 76

... Multicast_HASH0-0 – Multicast hash result 0 mask byte 0 CPU Address:h220 Accessed by CPU, serial interface (R/W) Bit [7:0] Default FF) ZL50418 HASH0_2 HASH0_1 HASH1_2 HASH1_1 HASH2_2 HASH2_1 HASH3_2 HASH3_1 Zarlink Semiconductor Inc. Data Sheet HASH0_0 HASH1_0 HASH2_0 HASH3_0 ...

Page 77

... Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) 14.6.18.7 Multicast_HASH2-0 – Multicast hash result 2 mask byte 0 CPU Address:h228 Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) 14.6.18.8 Multicast_HASH2-1 – Multicast hash result 2 mask byte 1 CPU Address:h229 Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) ZL50418 77 Zarlink Semiconductor Inc. Data Sheet ...

Page 78

... CPU Address:h300 Accessed by CPU Bit [7:0] Byte 0 of the CPU MAC address. (Default 00) 14.7.2 MAC1 – CPU Mac address byte 1 CPU Address:h301 Accessed by CPU Bit [7:0] Byte 1 of the CPU MAC address. (Default 00) ZL50418 MAC3 MAC2 MAC1 MAC0 78 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...

Page 79

... CPU frame interrupt. CPU frame buffer has data for CPU to read Bit [1]: • Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read Bit [2]: • Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Bit [7:3]: • Reserved ZL50418 79 Zarlink Semiconductor Inc. Data Sheet ...

Page 80

... CPU Address:h314 Accessed by CPU, serial interface (R/W) 14.7.13 INTP_MASK5 – Interrupt Mask for MAC Port 10,11 CPU Address:h315 Accessed by CPU, serial interface (R/W) 14.7.14 INTP_MASK6 – Interrupt Mask for MAC Port 12,13 CPU Address:h316 Accessed by CPU, serial interface (R/W) ZL50418 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 81

... RQSS [7:4]. 14.7.18 RQSS – Receive Queue Status CPU Address:h324 Accessed by CPU, serial interface (RO LQ3 LQ2 LQ1 ZL50418 FQ0 SQ3 SQ2 SQ1 4 3 LQ0 NeQ3 NeQ2 NeQ1 81 Zarlink Semiconductor Inc. Data Sheet 0 SQ0 0 NeQ0 ...

Page 82

... The default setting provide 300 seconds aging time. Aging time is based on the following equation: {AGETIME_TIME,AGETIME_LOW MAC entries in the memory X100µsec). Number of MAC entries = 32 K when used per Bank. Number of entries = 64 K when used per Bank. ZL50418 0 Tx Queue Agent 2 C (R/ (R/W) 82 Zarlink Semiconductor Inc. Data Sheet ...

Page 83

... Accessed by CPU, serial interface and Tos-d Tos-p PMCQ Bit [0]: • QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) ZL50418 0 0 FCBAT 2 C (R/ VF1c L 83 Zarlink Semiconductor Inc. Data Sheet ...

Page 84

... Select VLAN tag or TOS (IP packets preferentially picked to map transmit priority and drop priority ( Default = – Select VLAN Tag priority field over TOS - 1 – Select TOS over VLAN tag priority field ZL50418 2 C (R/ U2MR 84 Zarlink Semiconductor Inc. Data Sheet ...

Page 85

... Priority when the VLAN tag priority field is 5 (Default 0) 14.9.6 AVPMH – VLAN Priority Map Address h0AF, CPU Address:h505 Accessed by CPU, serial interface and VP7 ZL50418 2 C (R/ VP1 VP0 2 C (R/ VP3 VP2 2 C (R/ VP6 VP5 85 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 86

... Priority when the TOS field is 5 (Default 0) 14.9.9 TOSPMH – TOS Priority Map Address h0B2, CPU Address:h508 Accessed by CPU, serial interface and TP7 ZL50418 2 C (R/ TP1 2 C (R/ TP3 2 C (R/ TP6 TP5 86 Zarlink Semiconductor Inc. Data Sheet 0 TP0 0 TP2 ...

Page 87

... Frame drop priority when TOS field is 2 (Default 0) Bit [3]: Frame drop priority when TOS field is 3 (Default 0) Bit [4]: Frame drop priority when TOS field is 4 (Default 0) ZL50418 2 C (R/ FDV4 FDV3 FDV2 FDV1 2 C (R/ FDT4 FDT3 FDT2 FDT1 87 Zarlink Semiconductor Inc. Data Sheet 0 FDV0 0 FDT0 ...

Page 88

... Granularity 1 frame. (Default: h10 for 2 MB/bank or h08 for 1 MB/bank) 14.9.14 MCC – Multicast Congestion Control Address h0B7, CPU Address: 50D Accessed by CPU, serial interface and reaction period ZL50418 2 C (R/ Multicast Rate 2 C (R/ (R/ Multicast congest threshold 88 Zarlink Semiconductor Inc. Data Sheet ...

Page 89

... PRG[7:4] level. Also the threshold for initiating UC flow control. • Default: - H58 for memory 2 MB/bank; - H35 for 1 MB/bank; ZL50418 2 C (R/ Buffer reservation 2 C (R/ buffer reservation 89 Zarlink Semiconductor Inc. Data Sheet ...

Page 90

... Buffer reservation for class 3. Granularity 1. (Default 0) 14.9.20 C4RS – Class 4 Reserve Size Address h0BD, CPU Address 513 Accessed by CPU, serial interface and I 7 Class 4 FCB Reservation Buffer reservation for class 4. Granularity 1. (Default 0) ZL50418 2 C (R/ (R/ (R/ (R/ Zarlink Semiconductor Inc. Data Sheet ...

Page 91

... Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes, QOSC00: 512 bytes. Granularity when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes. ZL50418 2 C (R/ (R/ (R/ (R/W): C Address h0C1, CPU Address 517) C Address h0C2, CPU Address 518) C Address h0C3, CPU Address 519) 91 Zarlink Semiconductor Inc. Data Sheet ...

Page 92

... C Address h0C7, CPU Address 523 Address h0C8, CPU Address 524 Address h0C9, CPU Address 525 Address h0CA, CPU Address 526 Address h0CB, CPU Address 527 Address h0CC, CPU Address 528) 92 Zarlink Semiconductor Inc. Data Sheet ...

Page 93

... C Address h0CD, CPU Address 529 Address h0CE, CPU Address 52a Address h0CF, CPU Address 52b Address h0D0, CPU Address 52c Address h0D1, CPU Address 52d Address h0D2, CPU Address 52e) 93 Zarlink Semiconductor Inc. Data Sheet ...

Page 94

... Priority service allow flow control for the ports select this parameter set. [6]: Flow control pause best effort traffic only • QOSC42[5:0] – CREDIT_C2_G1 (CPU Address 541) • QOSC43[5:0] – CREDIT_C3_G1 (CPU Address 542) • QOSC44[5:0] – CREDIT_C4_G1 (CPU Address 543) ZL50418 94 Zarlink Semiconductor Inc. Data Sheet ...

Page 95

... Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when strict priority. QOSC49 programs the peak rate for gigabit port 2. See Programming QoS Register Application Note for more information. ZL50418 95 Zarlink Semiconductor Inc. Data Sheet ...

Page 96

... The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority can be ZL50418 c C (R/ Rate 2 C (R/ Rate 96 Zarlink Semiconductor Inc. Data Sheet ...

Page 97

... The chip allows the CPU to define the priority. Bits [3:0]: Priority setting, transmission + dropping, for logic port 0 Bits [7:4]: Priority setting, transmission + dropping, for logic port 1 (Default 00) ZL50418 2 C (R/ SER EFINE OGIC 2 C (R/ Priority 0 Drop 97 Zarlink Semiconductor Inc. Data Sheet ORT AND RIORITY ...

Page 98

... L 7 SER EFINE OGIC (R/ ELL NOWN 2 C (R/ Priority 0 Drop 98 Zarlink Semiconductor Inc. Data Sheet ORT AND RIORITY ORT AND RIORITY ORT AND RIORITY ORT NABLES OGIC ORT AND ...

Page 99

... ELL NOWN 2 C (R/ Priority 2 Drop K ELL NOWN 2 C (R/ Priority 4 Drop K ELL NOWN 2 C (R/ Priority 6 Drop 99 Zarlink Semiconductor Inc. Data Sheet OGIC ORT AND RIORITY OGIC ORT AND RIORITY OGIC ORT AND RIORITY ...

Page 100

... ANGE (R/ 15:8 EFINE ANGE (R/ 7:0 EFINE ANGE IGH (R/ 15:8 EFINE ANGE IGH (R/ EFINE ANGE RIORITY 2 C (R/ Range Transmit Priority Drop 100 Zarlink Semiconductor Inc. Data Sheet OGIC TO ORT NABLES ...

Page 101

... Vendor specified link status register address (null value means don’t use it) (Default 00). This is used if the Linkup bit position in the PHY is non-standard ZL50418 C Address h0C1, CPU Address 517) C Address h0C2, CPU Address 518) C Address h0C3, CPU Address 519 (R/ Vendor Spc. Reg Addr 101 Zarlink Semiconductor Inc. Data Sheet ...

Page 102

... When VLAN spanning tree is enable the registers ECR1Pn are NOT used to program the port spanning tree status. The port status is programmed using the Control Command Frame. ZL50418 2 C (R/ Duplex bit location 2 C (R/ Mul V- 102 Zarlink Semiconductor Inc. Data Sheet ...

Page 103

... Bit [6: – Operation code “10” for read command and “01” for write command Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. ZL50418 0 103 Zarlink Semiconductor Inc. Data Sheet ...

Page 104

... LED clock frequency (Default 0) • 00 =100 M/8 = 12.5 MHz • 100 M/32 = 125 MHz • Bit [7:5]: Reserved. Must be set to ‘0’ (Default 0) ZL50418 4 0 PHY address 2 C (R/ Clock rate Hold Time msec 01 = 100 M/ MHz 11 = 100 M/64 = 1.5625 MHz 104 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 105

... Source port to be mirrored. Use illegal port number to disable mirroring • Bit [5]: 1 – select ingress data 0 – select egress data • Bit [6]: Reserved • Bit [7]: Reserved must be set to '1' ZL50418 2 C (R/ register = 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... MIRROR2_DEST – Port Mirror destination CPU Address 703 Accessed by CPU, serial interface (R/W) (Default 00 Dest Port Select • Bit [4:0]: Port Mirror Destination When port mirroring is enable, destination port can not serve as a data port. ZL50418 106 Zarlink Semiconductor Inc. Data Sheet ...

Page 107

... Not busy (not reading configuration from I Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bit [5:4]: Device Signature 11: ZL50418 device ZL50418 Init Reset Bist BinP 107 Zarlink Semiconductor Inc. Data Sheet 0 BW ...

Page 108

... Chip initialization completed ZL50418 GIGA1 GIGA0 • 00 – 100 Mb MII mode • 01 – Reserved • 10 – GMII • 11 – PCS • 00 – 100 Mb MII mode • 01 – Reserved • 10 – GMII • 11 – PCS 108 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 109

... Reserved - 5’b10110 - Reserved - 5’b10111 - Reserved - 5’b11000 - Port 24 Operating mode/Neg status (CPU port) - 5’b11001 - Port 25 Operating mode/Neg status (Gigabit 1) - 5’b11010 - Port 26 Operating mode/Neg status (Gigabit Sig Giga Inkdn FE 109 Zarlink Semiconductor Inc. Data Sheet 1 0 Fdpx FcEn ...

Page 110

... Buffers Delay (Recommend) 100b 08h 4 Buffers Delay 101b 04h 3 Buffers Delay 110b 02h 2 Buffers Delay 111b 01h 1 Buffers Delay The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register. ZL50418 110 Zarlink Semiconductor Inc. Data Sheet ...

Page 111

... Normal operation. Bit [14] Reserved. Must be programmed with “0”. Bit [13] Speed selection (See bit 6 for complete details) Bit [12] Auto Negotiation Enable 1 = Enable auto-negotiation process Disable auto-negotiation process (Default). Bit [11:10] Reserved. Must be programmed with “0” ZL50418 111 Zarlink Semiconductor Inc. Data Sheet ...

Page 112

... Reserved. Always read back as “0” Bit [3] Reserved. Always read back as “1” Bit [2] Link Status 1 = Link is up Link is down. Bit [1] Reserved. Always read back as “0”. Bit [0] Reserved. Always read back as “1”. ZL50418 112 Zarlink Semiconductor Inc. Data Sheet ...

Page 113

... Reserved. Always read back as “0”. Bit [8:7] Pause. Bit [6] Half Duplex 1 = Support half duplex not support half duplex. Bit [5] Full duplex 1 = Support full duplex not support full duplex. Bit [4:0] Reserved. Always read back as “0”. ZL50418 113 Zarlink Semiconductor Inc. Data Sheet ...

Page 114

... Support 1000 full duplex operation (Default not support 1000 full duplex operation. Bit [14] 1000 Half Duplex 1 = Support 1000 half duplex operation (Default not support 1000 half duplex operation. Bit [13:0] Reserved. Always read back as “0”. ZL50418 114 Zarlink Semiconductor Inc. Data Sheet ...

Page 115

... 115 Zarlink Semiconductor Inc. Data Sheet ...

Page 116

... M12_ M14_ XD1 XEN XD1 XEN XD1 TXEN RXD1 TXEN RXD1 TXEN 116 Zarlink Semiconductor Inc. Data Sheet P_DA P_DA P_DA P_DA P_DA TSTO P_A0 P_A1 P_WE TA13 TA10 TA7 TA4 ...

Page 117

... Output I/O-TS with pullup Output Output with pull up Output Output with pull up Output with pull up 117 Zarlink Semiconductor Inc. Data Sheet Description Processor Bus Data Bit [15:0]. P_DATA[7:0] is used in 8-bit mode. Processor Bus Address Bit [2:0] CPU Bus-Write Enable CPU Bus-Read Enable ...

Page 118

... Output with pull up Output with pull up Output with pull up Output with pull up Output with pull up Output with pull up 118 Zarlink Semiconductor Inc. Data Sheet Description Frame Bank A Write Chip Select for upper layer of two layers SRAM configuration Frame Bank A Read Chip Select ...

Page 119

... Output Input w/ pull down Input w/ pull up Input w/ pull down Input w/ pull up Input w/ pull up 119 Zarlink Semiconductor Inc. Data Sheet Description MII Management Data Clock – (Common for all MII Ports [15:0]) MII Management Data I/O – (Common for all MII Ports –[15:0])) Reference Input Clock Ports [15:0] – ...

Page 120

... Input w/ pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up 120 Zarlink Semiconductor Inc. Data Sheet Description Receive Data Bit [9:0] Transmit Data Enable Transmit Error MII Mode Transmit Clock Gigabit Transmit Clock ...

Page 121

... I/O- TS with pull up I/O- TS with pull up I/O-TS Symbol I/O Input with pull down Input with pull down 121 Zarlink Semiconductor Inc. Data Sheet Description LED for Gigabit port 2 (receive + transmit) LED for Gigabit port 2 (full duplex + collision) LED for Gigabit port 2 System start operation ...

Page 122

... Input Power Power Power Ground Analog Power Analog Ground Input/ output Output Input/ output Input Output 122 Zarlink Semiconductor Inc. Data Sheet Description System Clock at 100 MHz +2.5 Volt DC Supply +3.3 Volt DC Supply Ground Analog +2.5 Volt DC Supply Analog Ground Scans the Collision signal of Home PHY ...

Page 123

... I/O NA Default 1 Default 1 Default 1 Recommend disable (0) with pull-down Default 1 Default 1 Default 1 123 Zarlink Semiconductor Inc. Data Sheet Description Reserved Pins. Leave unconnected. GIGA Link polarity 0 – active low 1 – active high RMII MAC Power Saving Enable 0 – No power saving 1 – power saving ...

Page 124

... Symbol I/O Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default: PCS 124 Zarlink Semiconductor Inc. Data Sheet Description Memory Size 0 - 256 256 total 128 128 total) EEPROM Installed 0 – EEPROM installed 1 – EEPROM not ...

Page 125

... I/O-TS = Input & Output signal with Tri-State driver I/O-OD =Input & Output signal with Open-Drain driver ZL50418 Symbol I/O Default: PCS Default: RMII Must be pulled-down Default: 111 Default: 111 125 Zarlink Semiconductor Inc. Data Sheet Description Giga1 Mode: G1_TXEN G1_TXER 0 0 MII 0 1 RSVD ...

Page 126

... SRAM application Output with pull up Frame Bank A Write Chip Select for upper bank of two layer SRAM application Output with pull up Frame Bank A Read Chip Select for one layer SRAM application 126 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 127

... Frame Bank B Read Chip Select for upper layer of two layers SRAM application Output MII Management Data Clock – (Common for all MII Ports [15:0]) I/O-TS with pull up MII Management Data I/O – (Common for all MII Ports –[15:0]) 127 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 128

... Input w/ pullup Receive Error Input w/ pulldown Carrier Sense Input w/ pullup Collision Detected Input w/ pullup Receive Clock Input w/ pullup Receive Data Bit [9:0] Output w/ pullup Transmit Data Enable Output w/ pullup Transmit Error Output Gigabit Transmit Clock 128 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 129

... LED for Gigabit port 2 (receive + transmit) I/O- TS with pull up LED for Gigabit port 2 (full duplex + collision) I/O- TS with pull up LED for Gigabit port 2 I/O- TS with pull up System start operation I/O- TS with pull up Start initialization I/O- TS with pull up EEPROM read OK 129 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 130

... Input with pull down Scan Enable 0 - Normal mode (open) Input with pull down 1 – Enable Test mode 0 - Normal mode (open) Input System Clock at 100 MHz Power +2.5 Volt DC Supply Power +3.3 Volt DC Supply 130 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 131

... Analog Ground Input Scans the Collision signal of Home PHY Input/ output Clock for scanning Home PHY collision and link Input Link up signal from Home PHY Input Reset Input Output Reset PHY NA Reserved Pins. Leave unconnected. 131 Zarlink Semiconductor Inc. Data Sheet Description ...

Page 132

... Reserved Default 1 FDB RAM depth ( layers) 0 – 2 layer 1 – 1 layer Default 1 CPU installed 0 – CPU installed 1 – CPU not installed 132 Zarlink Semiconductor Inc. Data Sheet Description (4 M total total) ...

Page 133

... Default: 111 Programmable delay for LA_CLK and LB_CLK from internal OE_CLK. The LA_CLK and LB_CLK delay from SCLK is the sum of the delay programmed in here and the delay in P_D[15:13]. Suggested value is 011. 133 Zarlink Semiconductor Inc. Data Sheet Description 0 0 MII 0 1 RSVD ...

Page 134

... B12 LA_A[15] K1 C12 LA_A[14] K2 A11 LA_A[13] K3 B11 LA_A[12] L1 C11 LA_A[11] L2 D11 LA_A[10] L3 E11 LA_A[9] M1 134 Zarlink Semiconductor Inc. Data Sheet Signal Name LA_OE0# LA_OE1# LB_D[63] LB_D[62] LB_D[61] LB_D[60] LB_D[59] LB_D[58] LB_D[57] LB_D[56] LB_D[55] LB_D[54] LB_D[53] LB_D[52] LB_D[51] LB_D[50] LB_D[49] LB_D[48] LB_D[47] ...

Page 135

... M[12]_RXD[1] AF17 AJ15 M[11]_RXD[1] AG17 AF15 M[10]_RXD[1] AG15 AJ13 M[9]_RXD[1] AF14 AF12 M[8]_RXD[1] AG13 AJ11 M[7]_RXD[1] AF11 135 Zarlink Semiconductor Inc. Data Sheet Signal Name LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] LB_D[27] LB_D[26] LB_D[25] LB_D[24] LB_D[23] LB_D[22] M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] ...

Page 136

... M[5]_TXD[0] H29 AH6 M[4]_TXD[0] H28 AF4 M[3]_TXD[0] H27 AH4 M[2]_TXD[0] J29 AG2 M[1]_TXD[0] J28 AE2 M[0]_TXD[0] J27 136 Zarlink Semiconductor Inc. Data Sheet Signal Name M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV M[0]_CRS_DV RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ...

Page 137

... M25_RXD[4] E25 AA27 M25_RXD[3] G29 AB29 M25_RXD[2] F29 AB28 M25_RXD[1] F26 AB27 M25_RXD[0] E26 R26 M25_TX_ER F25 137 Zarlink Semiconductor Inc. Data Sheet Signal Name M26_RXD[8] M26_RXD[7] M26_RXD[6] M26_RXD[5] M26_RXD[4] M26_RXD[3] M26_RXD[2] M26_RXD[1] M26_RXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M26_TXD[9] ...

Page 138

... C19 OE_CLK2 M16 B19 OE_CLK1 M17 A19 OE_CLK0 M18 R13 VSS F16 R14 VSS F17 R15 VSS N6 138 Zarlink Semiconductor Inc. Data Sheet Signal Name BIST_DONE/TSTOUT[15] BIST_IN_PRC/TST0UT[14] MCT_ERR/TSTOUT[13] FCB_ERR/TSTOUT[12] CHECKSUM_OK/TSTOUT[11 ] INIT_START/TSTOUT[10] INIT_DONE/TSTOUT[9] VSS VSS VDD VDD VDD VDD VDD VDD VDD ...

Page 139

... VSS F14 M12 VSS F15 M13 VSS M14 VSS M15 VSS P17 VSS P18 VSS R12 VSS 139 Zarlink Semiconductor Inc. Data Sheet Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ...

Page 140

... C14 LA_A[20] A13 LA_A[19] B13 LA_A[18] C13 LA_A[17] A12 LA_A[16] B12 LA_A[15] C12 LA_A[14] A11 LA_A[13] B11 LA_A[12] C11 LA_A[11] D11 LA_A[10] 140 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. A9 LA_OE0# B9 LA_OE1# F4 LB_D[63] F5 LB_D[62] G4 LB_D[61] G5 LB_D[60] H4 LB_D[59] H5 LB_D[58] J4 LB_D[57] ...

Page 141

... AJ25 RESERVED AF24 RESERVED AH23 RESERVED AE19 RESERVED AF21 M[15]_RXD[1] AJ19 M[14]_RXD[1] AF18 M[13]_RXD[1] AJ17 M[12]_RXD[1] AJ15 M[11]_RXD[1] AF15 M[10]_RXD[1] AJ13 M[9]_RXD[1] 141 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. M1 LB_D[34] M2 LB_D[33] M3 LB_D[32] U4 LB_D[31] U5 LB_D[30] V4 LB_D[29] V5 LB_D[28] W4 LB_D[27] W5 LB_D[26] ...

Page 142

... AH13 M[9]_RXD[0] AE12 M[8]_RXD[0] AH11 M[7]_RXD[0] AH9 M[6]_RXD[0] AE9 M[5]_RXD[0] AH8 M[6]_TXD[0] AF7 M[5]_TXD[0] AH6 M[4]_TXD[0] AF4 M[3]_TXD[0] 142 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. AG13 M[9]_CRS_DV AF11 M[8]_CRS_DV AG11 M[7]_CRS_DV AG9 M[6]_CRS_DV AF8 M[5]_CRS_DV AG7 M[4]_CRS_DV AF5 M[3]_CRS_DV ...

Page 143

... W29 RESERVED W28 RESERVED W27 M25_RXD[9] Y29 M25_RXD[8] Y28 M25_RXD[7] Y25 M25_RXD[6] AA29 M25_RXD[5] AA28 M25_RXD[4] AA27 M25_RXD[3] 143 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. J29 RESERVED J28 RESERVED J27 M26_RXD[9] K29 M26_RXD[8] K28 M26_RXD[7] K27 M26_RXD[6] L29 M26_RXD[5] ...

Page 144

... N15 VSS C19 P_DATA15 B19 P_DATA14 A19 P_DATA13 P12 VSS P13 VSS P14 VSS P15 VSS P16 VSS 144 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. F29 M26_RXCLK F26 M26_TX_EN E26 M26_TX_ER F25 M26_TXCLK E24 BIST_DONE/TSTOUT[15] D24 BIST_IN_PRC/TST0UT[14] D25 MCT_ERR/TSTOUT[13] ...

Page 145

... VSS U16 VSS U17 VSS M12 VSS M13 VSS M14 VSS M15 VSS P17 VSS P18 VSS R12 VSS 145 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. M16 VSS M17 VSS M18 VSS F16 VCC F17 VCC N6 VCC P6 VCC R6 VCC ...

Page 146

... Thermal resistance between junction and case jc ZL50418 - +150  +125  +2. +2. -0 (VCC + 3 -40C to +85 C AMBIENT Min. 2.4 2.0 < VCC) IN 146 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Unit 100 MHz 350 mA 1400 mA V 0.4 V VCC + 2 ...

Page 147

... ZL50418 Min. Tri-Stated R3 Inputs R2 Min. Typ Table 16 - Reset & Bootstrap Timing 147 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Unit 6.6 C/W Outputs Note: RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising 1 edge of RESIN# ...

Page 148

... Hold time (SCLK=100 Mhz) Symbol Min. Max Table 17 - Write Cycle 148 Zarlink Semiconductor Inc. Data Sheet ADDR1 least WH 2 SCLKs T DH DATA Refer to Figure 19 At least 2 SCLK At least 3 SCLK ...

Page 149

... DV DI 2ns Invalid time (SCLK=100 Mhz) Symbol Min. Max least 2 SCLK least 3 SCLK Table 18 - Read Cycle 149 Zarlink Semiconductor Inc. Data Sheet ADDR1 least 2 SCLKs DATA Refer to Figure 20 ...

Page 150

... Figure 21 - Local Memory Interface – Input Setup and Hold Timing LA_WE[1:0]# LA_OE[1:0]# Figure 22 - Local Memory Interface - Output Valid Delay Timing ZL50418 LA_CLK L1 L2 LA_D[63:0] LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_ADSC# L7-max L7-min #### L8-max L8-min L9-max L9-min LA_WE# L10-max L10-min LA_OE# 150 Zarlink Semiconductor Inc. Data Sheet ...

Page 151

... Local SBRAM Memory Interface Figure 23 - Local Memory Interface – Input Setup and Hold Timing ZL50418 Parameter Min. (ns) 4 1.5 1 LB_CLK L1 L2 LB_D[63:0] 151 Zarlink Semiconductor Inc. Data Sheet -100 MHz Note Max. (ns ...

Page 152

... L4-max L4-min L6-max L6-min L8-max L8-min L9-max L9-min L10-max L10-min L11-max L11-min -100 MHz Min. (ns) Max. (ns) 4 1.5 1 152 Zarlink Semiconductor Inc. Data Sheet Note ...

Page 153

... M[15:0]_TXD[1:0] Output Delay Time Table Characteristics – Reduced Media Independent Interface ZL50418 M_CLKI M6-max M6-min 15 M7-max M7-min M_CLKI M2 M[23:0]_RXD Parameter Min. (ns 153 Zarlink Semiconductor Inc. Data Sheet -50 MHz Note Max. (ns ...

Page 154

... M25_TXCLK G12-max G12-min G13-max G13-min G14-max G14-min M25_TX_ER Figure Characteristics- GMII M25_RXCLK -125 Mhz Min. (ns 154 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns 6 ...

Page 155

... M25_TXD[9:0] Output Delay Time Symbol Parameter T2 M25_RXD[9:0] Input Setup Time T3 M25_RXD[9:0] Input Hold Time ZL50418 M25_TXCLK TIMIN Min. (ns) 1 Table 23 - Output Delay Timing Min. (ns Table 24 - Input Setup Timing 155 Zarlink Semiconductor Inc. Data Sheet TIMAX T3 Max. (ns) Note Max. (ns) Note ...

Page 156

... Table Characteristics – Gigabit Media Independent Interface ZL50418 M26_TXCLK G12-max G12-min G13-max G13-min G14-max G14-min M26_TX_ER Figure Characteristics- GMII M26_RXCLK -125 Mhz Min. (ns 156 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns ...

Page 157

... Mhz Min. (ns TIMIN TIMAX Figure 34 - Gigabit TBI Interface Timing Min. (ns) 1 Table 26 - Output Delay Timing Min. (ns Table 27 - Input Setup Timing 157 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns) 6 Max. (ns) Note Max ...

Page 158

... Figure 36 - SCANLINK SCANCOL Output Delay Timing SCANCLK SCANLINK SCANCOL Figure 37 - SCANLINK, SCANCOL Setup Timing ZL50418 LED_CLK LE5-max LE5-min LE6-max LE6-min LED_BIT Variable FREQ. Min. (ns C5-max C5-min C7-max C7-min 158 Zarlink Semiconductor Inc. Data Sheet Max. (ns) Note ...

Page 159

... MDIO Input Setup and Hold Timing Figure 38 - MDIO Input Setup and Hold Timing ZL50418 Parameter Min. (ns MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 39 - MDIO Output Delay Timing 159 Zarlink Semiconductor Inc. Data Sheet -25 MHz Max. (ns) Note ...

Page 160

... S2 S1 SDA 2 Figure Input Setup Timing SCL S3-max S3-min SDA 2 Figure Output Delay Timing Parameter Min. (ns usec 2 Table Timing 160 Zarlink Semiconductor Inc. Data Sheet 1 MHz Max. (ns) Note KHz Max. (ns) Note 6 usec ...

Page 161

... AutoFd output delay time D4 Strobe low time D5 Strobe high time ZL50418 Figure 42 - Serial Interface Setup Timing D3-max D3-min Parameter Min. (ns Table 32 - Serial Interface Timing 161 Zarlink Semiconductor Inc. Data Sheet D5 D2 Max. (ns) Note 100 pf L ...

Page 162

NOTE: 1. CONTROLLING DIMENSIONS ARE DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE NUMBER OF ...

Page 163

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...