zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 85
zl50415
Manufacturer Part Number
zl50415
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50415.pdf
(163 pages)
- Current page: 85 of 163
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14.9.4
I
Accessed by CPU, serial interface and I
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit
priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature
allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0
of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used
inside the ZL50418. When the packet goes out it carries the original priority.
14.9.5
I
Accessed by CPU, serial interface and I
Map VLAN priority into eight level transmit priorities:
14.9.6
I
Accessed by CPU, serial interface and I
2
2
2
C Address h0AD; CPU Address:h503
C Address h0AE, CPU Address:h504
C Address h0AF, CPU Address:h505
AVPML – VLAN Tag Priority Map
AVPMM – VLAN Priority Map
AVPMH – VLAN Priority Map
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
Bit [0]:
Bit [3:1]:
Bit [6:4]:
Bit [7]:
7
7
VP5
7
6
VP2
6
VP7
Priority when the VLAN tag priority field is 2 (Default 0)
Priority when the VLAN tag priority field is 3 (Default 0)
Priority when the VLAN tag priority field is 4 (Default 0)
Priority when the VLAN tag priority field is 5 (Default 0)
Priority when the VLAN tag priority field is 0 (Default 0)
Priority when the VLAN tag priority field is 1 ( Default 0)
Priority when the VLAN tag priority field is 2 (Default 0)
5
VP4
5
VP1
4
2
2
2
C (R/W)
C (R/W)
C (R/W)
4
3
3
Zarlink Semiconductor Inc.
ZL50418
VP6
2
VP3
85
VP0
1
2
0
0
VP2
1
VP5
0
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