zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 17

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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The format of the Control Frame is described in the processor interface application note.
2.3.4
In unmanaged mode, the ZL50418 can be configured by EEPROM (24C02 or compatible) via an I
boot time or via a synchronous serial interface during operation.
2.4
The I
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps.
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer.
Figure 3 depicts the data transfer format.
2.4.1
Generated by the master (in our case, the ZL50418). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I
free both lines are High.
2.4.2
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.4.3
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.4.4
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
Learn MAC address
Delete MAC address
Delete IP Multicast address
New VLAN port
Age out VLAN port
Response to search MAC address request from CPU
Response to search IP Multicast address request from CPU
2
C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
I
2
C Interface
Unmanaged Mode
Start Condition
Address
Data Direction
Acknowledgment
START
SLAVE ADDRESS
Data transfer is performed between master and slave IC using a request /
Figure 3 - Data Transfer Format for I
RW
ACK
Zarlink Semiconductor Inc.
DATA1 (8bits)
ZL50418
17
ACK
DATA 2
2
C Interface
ACK
DATA M
ACK
STOP
2
Data Sheet
C interface at
2
C bus is