zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 125

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Notes:
# =Active low signal
Input =Input signal
In-ST = Input signal with Schmitt-Trigger
Output =Output signal (Tri-State driver)
Out-OD=Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD =Input & Output signal with Open-Drain driver
F26, E26
AE20, AJ18, AJ21,
AJ16, AJ14, AE14,
AJ12, AE11, AJ10, AJ8,
AE8, AJ6, AE5, AJ4,
AG1, AE1
C21
C19, B19, A19
C20, B20, A20
Ball No(s)
G1_TXEN, G1_TXER
M[15:0] TXEN
P_D[9]
P_D[15:13]
P_D[12:10]
Symbol
Zarlink Semiconductor Inc.
ZL50418
125
Default: PCS
Default: RMII
Must be pulled-down
Default: 111
Default: 111
I/O
Giga1
Mode:
G1_TXEN G1_TXER
RSVD
GMII
PCS
0 – GPSI
1 – RMII
Reserved - Must be
pulled-down
Programmable delay for
internal OE_CLK from
SCLK input. The
OE_CLK is used for
generating the OE0 and
OE1 signals
Suggested value is 001.
Programmable delay for
LA_CLK and LB_CLK
from internal OE_CLK .
The LA_CLK and
LB_CLK delay from
SCLK is the sum of the
delay programmed in
here and the delay in
P_D[15:13].
Suggested value is 011.
0
0
1
1
Description
Data Sheet
0
1
0
1
MII